mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
6be73fa6b7
- Changed the interface from ribp to rib in soc_topology.json and related files. - Updated formal.mk to reflect the new rib2apb naming convention. - Implemented rib2apb module to handle RIB to APB communication. - Modified bus.sv to integrate the new rib2apb module and adjust signal assignments accordingly. - Updated testbench files to use the new rib interface and validate the RIB to APB functionality. - Created rib2apb_tb for testing the direct RIB to APB bridge. - Adjusted script tools and test scripts to accommodate the new naming and structure.
81 lines
2.8 KiB
Systemverilog
81 lines
2.8 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "mmap_define.svh"
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`include "uart_define.svh"
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`include "pwm_define.svh"
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`include "ps2_define.svh"
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`include "user_extensions.svh"
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`include "soc_irq_config.svh"
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module ip_apb_wrapper (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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input logic clk_aud_i,
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input logic rst_aud_n_i,
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input logic tmr_capch_i,
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rib_if.slave rib,
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uart_if.dut uart,
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pwm_if.dut pwm,
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ps2_if.dut ps2,
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input logic [`USER_IPSEL_WIDTH-1:0] ip_sel_i,
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user_gpio_if.user_ip user_gpio,
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output logic [`SOC_IRQ_APB_WIDTH-1:0] irq_o
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// verilog_format: on
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);
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// Generated timed and pure scalar APB interfaces preserve FPGA compatibility.
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`include "soc_apb_interfaces.svh"
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// Low-frequency peripherals retain their dedicated interfaces.
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rtc_if u_rtc_if (
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clk_aud_i,
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rst_aud_n_i
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);
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wdg_if u_wdg_if (clk_aud_i);
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tmr_if u_tmr_if (clk_aud_i);
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assign u_tmr_if.capch_i = tmr_capch_i;
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`include "soc_apb_bridges.svh"
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// verilog_format: off
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apb4_archinfo u_apb4_archinfo (u_archinfo_apb_if);
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apb4_rng u_apb4_rng (u_rng_apb_if);
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apb4_uart #(.FIFO_DEPTH(32)) u_apb4_uart (u_uart1_apb_if, uart);
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apb4_pwm u_apb4_pwm (u_pwm_apb_if, pwm);
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apb4_ps2 u_apb4_ps2 (u_ps2_apb_if, ps2);
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apb4_rtc u_apb4_rtc (u_rtc_apb_if, u_rtc_if);
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apb4_wdg u_apb4_wdg (u_wdg_apb_if, u_wdg_if);
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apb4_crc u_apb4_crc (u_crc_apb_if);
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apb4_tmr u_apb4_tmr (u_tmr_apb_if, u_tmr_if);
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// verilog_format: on
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// Generated IRQ ownership and core-vector bit assignments are topology checked.
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`include "soc_apb_irq_bindings.svh"
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rib2apb u_rib2apb (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.rib (rib),
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`include "soc_apb_connections.svh"
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);
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user_ip_wrapper u_user_ip_wrapper (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.sel_i (ip_sel_i),
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.gpio (user_gpio),
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.apb (u_user_ip_apb_if)
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);
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endmodule
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