mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
bc48cec74a
Integrate the Tiny RCU, normalized REF24 control, external-input profiles, single PLL backend, SYS/MEM/PCLK clocks, CPU-only WFI gating, peripheral lifecycle control and retained debug behavior. Keep CPU and all 32 main SRAM macros on SYS and the six private Crypto macros on PCLK. Add the handwritten RCU register/HAL contract, RS_EBUSY, bounded SDK operations and focused firmware. Preserve shared-IP defaults and the ICS55/PLL SAFE24 boot and explicit IHP130/no-PLL compatibility profiles. Use APB/AXI domain bridges and source-owned response holders to preserve backpressured responses, complete aborted bursts and prevent stale replay. Verify production DMA source-reset drain and common XPI endpoint reset with extracted integration bindings and an independent scoreboard. Add source-bound macro/clock audits, SAFE24 observational STA constraints and commercial-adapter host checks. No P8 functionality or operating-point qualification is included. See TINY-R2-P7 in docs/ip/tiny-soc.md. Validation: 54 P7 directed tests pass, including both simulators, ten source-reset ratio runs and two expected-negative drain mutations. RTL format/style, clock/reset inventory, Ruff and both Tiny PDK PR dry-runs pass. Retained 06-00 synthesis and strict netlist boots pass for both PDKs; STA remains negative and observational. Source comparison confirms only the follow-up tests changed after that backend campaign. Evidence: build/ics55-tiny-2026-10-14-06-00-ff4b5cef6eb5/meta/ tiny-r2-p7-source-reset/summary.json. Earlier firmware, HAL and compatibility results and the non-clean full-suite attempt retain their original attribution. Full Icarus firmware is deferred to final Tiny qualification; this commit does not constitute human phase acceptance or physical signoff.
365 lines
19 KiB
Python
365 lines
19 KiB
Python
#!/usr/bin/env python3
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"""Source-bound Tiny ICS55 evidence and a fail-closed SAFE24 netlist audit."""
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from __future__ import annotations
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import argparse
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from datetime import datetime, timezone
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import hashlib
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from pathlib import Path
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import re
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import sys
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import tarfile
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ROOT = Path(__file__).resolve().parents[1]
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sys.path.insert(0, str(ROOT))
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from scripts import tiny_r2_baseline as b # noqa: E402
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from scripts.config_key import variant_id # noqa: E402
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from scripts.tiny_r2_feasibility import timing_metrics, path_slack # noqa: E402
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PHASE = "TINY-ICS55-P1"
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RAM = "ics55_ecos_sram_1024x32_m8"
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def inspect_clock_source(leaves: list[dict], system: str, reference: str,
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constants: dict) -> list[dict]:
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"""Prove the supported SAFE24 pad/buffer path, rejecting unknown logic.
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This deliberately recognizes only the selected ICS55 input receiver and
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non-inverting clock buffer. A future clock mux/gate needs its own review.
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Inout drivers are included so a second driver on REF24 cannot be hidden.
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"""
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drivers = {}
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for cell in leaves:
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for port, bits in cell["ports"].items():
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if cell["directions"].get(port) in ("output", "inout"):
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for bit in bits:
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drivers.setdefault(bit, []).append((cell, port))
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def scalar(cell, port):
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bits = cell["ports"].get(port, [])
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if len(bits) != 1:
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raise ValueError(f"missing scalar clock-path pin: {cell['path']}/{port}")
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return bits[0]
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trace, seen = [], set()
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cursor = system
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while True:
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if cursor in constants or cursor in ("x", "z") or cursor in seen:
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raise ValueError("constant, unknown or cyclic SYS clock source")
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seen.add(cursor)
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candidates = drivers.get(cursor, [])
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if len(candidates) != 1:
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raise ValueError("SYS clock source has missing or multiple drivers")
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cell, port = candidates[0]
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trace.append({"path": cell["path"], "type": cell["type"], "output": port})
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if cell["type"] == "BUFX0P7H7R" and port == "Y":
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cursor = scalar(cell, "A")
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elif cell["type"] == "P65_1233_PBMUX" and port == "C":
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if scalar(cell, "PAD") != reference:
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raise ValueError("SYS input receiver is not connected to external REF24")
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if any(constants.get(scalar(cell, pin)) != value
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for pin, value in (("IE", 1), ("OE", 0), ("CS", 1))):
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raise ValueError("REF24 pad is not a constant-enabled CMOS input")
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if drivers.get(reference) != [(cell, "PAD")]:
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raise ValueError("external REF24 has an additional internal driver")
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return trace
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else:
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raise ValueError(f"unsupported SYS clock source: {cell['type']}/{port}")
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def verify_locked_views(root: Path) -> dict:
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"""Check derived cache bytes against the unchanged locked archives."""
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lock = b.read_json(root / "dependencies/dependencies.lock.json")
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verified = {}
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for key in ("pdk_ics55_h7cr_liberty", "pdk_ics55_sram_1024x32_m8", "pdk_ics55_sram_4096x32_m8"):
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spec = lock["archives"][key]
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path = root / spec["destination"]
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if b.sha256(path) != spec["sha256"]:
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raise ValueError(f"locked archive changed: {key}")
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package = key.replace("pdk_ics55_sram_", "ics55_ecos_sram_")
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seen = set()
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with tarfile.open(path) as archive:
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for member in archive:
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if not member.isfile():
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continue
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relative = Path(member.name)
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if relative.is_absolute() or ".." in relative.parts:
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raise ValueError("unsafe archive view name")
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target = None
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if key == "pdk_ics55_h7cr_liberty":
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for corner, tokens in (("tt", ("tt", "1p2", "25")), ("ss", ("ss", "1p08", "125"))):
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if member.name.endswith(".lib") and all(t in member.name.lower() for t in tokens):
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target = root / f".cache/retrosoc/pdk/ics55/ics55_h7cr_{corner}.lib"
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else:
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if relative.parts[0] == package:
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relative = Path(*relative.parts[1:])
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if relative.parts and relative.parts[0] in ("lib", "verilog"):
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target = root / ".cache/retrosoc/pdk/ics55/sram" / package / relative
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if target is not None:
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if not target.is_file() or hashlib.sha256(archive.extractfile(member).read()).hexdigest() != b.sha256(target):
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raise ValueError(f"cached view differs from locked archive: {target}")
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seen.add(str(target))
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if len(seen) != (2 if key == "pdk_ics55_h7cr_liberty" else 11):
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raise ValueError(f"incomplete locked view set: {key}")
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verified[key] = {"archive": b.artifact(path), "views": sorted(seen)}
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from physical.pdk.prepare_ics55_sim_model import patch_muxi2_models, VERILATOR_LINT_OFF, VERILATOR_LINT_ON
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pdk = root / lock["sources"]["pdk_ics55"]["destination"]
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original = pdk / "IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/verilog/ics55_LLSC_H7CR.v"
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patched, _ = patch_muxi2_models(original.read_text())
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expected = VERILATOR_LINT_OFF + patched.rstrip() + "\n" + VERILATOR_LINT_ON
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model = root / ".cache/retrosoc/pdk/ics55/ics55_h7cr_functional.v"
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if model.read_text() != expected:
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raise ValueError("standard-cell functional model differs from the owned locked-source transform")
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verified["functional_cells"] = b.artifact(model)
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return verified
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def expand_netlist(document: dict) -> tuple:
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"""Resolve hierarchy aliases without assigning a product clock contract."""
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modules = document["modules"]
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top = "retrosoc_tiny_asic"
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leaves = []
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boundaries = {}
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aliases = {}
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def canonical(bit):
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if bit in aliases:
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aliases[bit] = canonical(aliases[bit])
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return aliases[bit]
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return bit
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def alias(a, other):
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a, other = canonical(a), canonical(other)
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if a == other:
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return
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if a in ("0", "1", "x", "z"):
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a, other = other, a
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if a in ("0", "1", "x", "z"):
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raise ValueError("conflicting constants at a hierarchy boundary")
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aliases[a] = other
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def visit(module_name, scope, bound):
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module = modules[module_name]
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mapping = {}
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for port, bits in bound.items():
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declaration = module["ports"][port]
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for local, external in zip(declaration["bits"], bits):
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if isinstance(local, str):
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if declaration["direction"] == "output":
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alias(external, local)
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elif local in mapping:
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alias(external, mapping[local])
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else:
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mapping[local] = external
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def net(bit):
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return bit if isinstance(bit, str) else mapping.get(bit, f"{scope}:{bit}")
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for name, cell in module.get("cells", {}).items():
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ports = {port: [net(bit) for bit in bits] for port, bits in cell["connections"].items()}
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kind = cell["type"]
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path = f"{scope}/{name}"
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attrs = modules.get(kind, {}).get("attributes", {})
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if kind in modules and not int(str(attrs.get("blackbox", "0")), 2):
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boundaries[path] = {"path": path, "type": kind, "ports": ports}
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visit(kind, path, ports)
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else:
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directions = cell.get("port_directions", {
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p: decl["direction"] for p, decl in modules.get(kind, {}).get("ports", {}).items()
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})
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leaves.append({"path": path, "type": kind, "ports": ports,
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"directions": directions})
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visit(top, top, {})
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for c in [*leaves, *boundaries.values()]:
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for port, bits in c["ports"].items():
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c["ports"][port] = [canonical(bit) for bit in bits]
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return modules, top, leaves, canonical, boundaries
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def inspect_netlist(document: dict) -> dict:
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# Keep the original P1 parked-PLL/direct-SYS contract fail-closed.
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modules, top, leaves, canonical, _ = expand_netlist(document)
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clock = modules[top]["cells"]["u_clock_buffer"]["connections"]["clk_o"]
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if len(clock) != 1 or not isinstance(clock[0], int):
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raise ValueError("missing live SYS clock")
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system = canonical(f"{top}:{clock[0]}")
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if system in ("0", "1", "x", "z"):
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raise ValueError("SYS is not a live clock net")
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all_ram = [c for c in leaves if c["type"] == RAM]
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crypto_names = {f"u_soc.u_crypto.u_storage.gen_bank[{n}].gen_macro.u_sram.u_mem"
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for n in range(6)}
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crypto = [c for c in all_ram if any(c["path"].replace("/", ".").endswith("." + name)
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for name in crypto_names)]
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observed_crypto = {name for name in crypto_names for c in crypto
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if c["path"].replace("/", ".").endswith("." + name)}
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if len(all_ram) != 38 or len(crypto) != 6 or observed_crypto != crypto_names:
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raise ValueError("Tiny P6 requires exactly 32 main SRAM and six private Crypto macros")
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if any(c["ports"].get("CLK") != [system] for c in crypto):
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raise ValueError("private Crypto SRAM does not use SAFE24 PCLK")
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ram = [c for c in all_ram if c not in crypto]
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pll = [c for c in leaves if c["type"] == "PLL_TOP"]
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if any(c["type"] == "ics55_ecos_sram_4096x32_m8" for c in leaves):
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raise ValueError("Tiny instantiated the unsupported 16 KiB SRAM interface stub")
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if len(ram) != 32 or len(pll) != 1:
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raise ValueError("expected 32 main SRAM macros and one PLL")
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expected_ram = {f"u_soc.u_sram.gen_group[{g}].u_group.gen_bank[{n}].u_ram.u_mem"
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for g in range(4) for n in range(8)}
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observed_ram = {next((name for name in expected_ram
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if c["path"].replace("/", ".").endswith("." + name)), "") for c in ram}
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if observed_ram != expected_ram:
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raise ValueError("Tiny P4 SRAM group/macro hierarchy is missing or stale")
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if any(c["ports"].get("CLK") != [system] for c in ram):
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raise ValueError("main SRAM does not share direct SYS")
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constants = {"0": 0, "1": 1}
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for c in leaves:
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if c["type"] in ("TIELOH7R", "TIEHIH7R"):
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for bit in c["ports"]["Z"]:
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constants[bit] = int(c["type"] == "TIEHIH7R")
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ref_port = modules[top]["ports"].get("extclk_i_pad", {})
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ref_bits = ref_port.get("bits", [])
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if (ref_port.get("direction") not in ("input", "inout") or len(ref_bits) != 1
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or not isinstance(ref_bits[0], int)):
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raise ValueError("missing live external REF24 input port")
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reference = canonical(f"{top}:{ref_bits[0]}")
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if reference in constants or reference in ("x", "z"):
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raise ValueError("external REF24 input is tied off or unknown")
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clock_path = inspect_clock_source(leaves, system, reference, constants)
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enable = pll[0]["ports"].get("EN", [])
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if len(enable) != 1 or constants.get(enable[0]) != 0:
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raise ValueError("PLL enable is not proven constant zero")
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cpu = [c for c in leaves if "u_hazard3_cpu_2port" in c["path"]
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and ("CK" in c["ports"] or "CKN" in c["ports"])]
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if not cpu or any(c["ports"].get("CK", c["ports"].get("CKN")) != [system] for c in cpu):
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raise ValueError("CPU sequential clocks do not share direct SYS")
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pll_outputs = {bit for name in ("CKOUT1", "CKOUT2", "CKTST") for bit in pll[0]["ports"].get(name, [])}
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if system in pll_outputs:
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raise ValueError("PLL drives SYS")
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return {"system_net": system,
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"system_clock_source": {"port": "extclk_i_pad", "net": reference, "path": clock_path},
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"cpu_clocked_cells": len(cpu),
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"sram": [{"path": c["path"], "clock": c["ports"]["CLK"]} for c in ram],
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"crypto_sram": [{"path": c["path"], "clock": c["ports"]["CLK"]} for c in crypto],
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"pll": pll[0], "pll_enable": 0, "qualification": "SAFE24 digital connectivity only"}
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def check_configuration(variant: Path, path: Path) -> None:
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manifest = b.configuration(variant)
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if manifest["configuration"]["PDK"] != "ICS55":
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raise ValueError("ICS55 platform evidence cannot consume another PDK")
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config = dict(line.split("=", 1) for line in path.read_text().splitlines() if "=" in line)
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for key, value in {"PDK": "ICS55", "SOC": "TINY", "HAVE_PLL": "YES",
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"HAVE_SRAM_MACRO": "YES", "SRAM_SIZE_KIB": "128",
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"TOP_DESIGN": "retrosoc_tiny_asic", "PERIOD_PS": "41667"}.items():
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if config.get(key) != value:
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raise ValueError(f"consumed netlist configuration mismatch: {key}")
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values = [f"{k}={v}" for k, v in manifest["configuration"].items()
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if k not in ("SIMU", "SYNTH", "SYNTH_RECIPE", "STA")]
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expected = variant_id(manifest["profile"], values, ROOT / "dependencies/dependencies.lock.json",
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"2000-01-01-00-00").rsplit("-", 1)[1]
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if config.get("CONFIG_DIGEST") != expected or variant.name.rsplit("-", 1)[1] != expected:
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raise ValueError("consumed configuration digest mismatch")
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def verify_netlist(variant: Path, netlist: Path, config: Path, output: Path) -> dict:
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check_configuration(variant, config)
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report = b.read_json(output)
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if report.get("status") != "passed" or report.get("phase") != PHASE:
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raise ValueError("missing successful structural audit")
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if report.get("audit_script") != b.artifact(Path(__file__)):
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raise ValueError("structural audit was produced by another script")
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expected = [netlist, Path(str(netlist) + ".json"), config]
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if report.get("inputs") != [b.artifact(path) for path in expected]:
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raise ValueError("missing or changed consumed netlist artifacts")
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return report
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def main() -> int:
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parser = argparse.ArgumentParser(description=__doc__)
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parser.add_argument("--variant-root", type=Path, required=True)
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parser.add_argument("action", choices=("capture", "audit-netlist", "verify-netlist", "report"))
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parser.add_argument("--netlist", type=Path)
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parser.add_argument("--config", type=Path)
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parser.add_argument("--output", type=Path)
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args = parser.parse_args()
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variant = args.variant_root.resolve()
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parent = variant / "meta/tiny-ics55-p1"
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try:
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if args.action == "capture":
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directory = b.new_attempt(parent, "inputs-")
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b.dump(parent / "latest-inputs.json", {"path": str(directory / "identity.json")})
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b.dump(directory / "identity.json", {"phase": PHASE, "status": "capturing"})
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inputs = b.source_inputs(ROOT, "ICS55")
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for path in (ROOT / "tests").rglob("*"):
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if path.is_file() and path.suffix in (".py", ".sv", ".svh"):
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inputs[str(path.relative_to(ROOT))] = b.sha256(path)
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views = verify_locked_views(ROOT)
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identity = {"phase": PHASE, "status": "captured", "created_at": datetime.now(timezone.utc).isoformat(), "views": views,
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"source": b.snapshot(ROOT, directory, inputs), "tools": b.tools_identity(ROOT)}
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if any(b.sha256(ROOT / name) != digest for name, digest in inputs.items()):
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raise ValueError("source changed while capturing inputs")
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b.dump(directory / "identity.json", identity)
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b.dump(parent / "latest-inputs.json", {"path": str(directory / "identity.json")})
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elif args.action in ("audit-netlist", "verify-netlist"):
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if not all((args.netlist, args.config, args.output)):
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parser.error("netlist actions require --netlist, --config and --output")
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check_configuration(variant, args.config)
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if args.action == "audit-netlist":
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net_json = Path(str(args.netlist) + ".json")
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report = {"phase": PHASE, "status": "passed", "audit_script": b.artifact(Path(__file__)),
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"binding": inspect_netlist(b.read_json(net_json)),
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"inputs": [b.artifact(p) for p in (args.netlist, net_json, args.config)]}
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b.dump(args.output, report)
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else:
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verify_netlist(variant, args.netlist, args.config, args.output)
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else:
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b.dump(parent / "report.json", {"phase": PHASE, "status": "incomplete"})
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identity = b.read_json(Path(b.read_json(parent / "latest-inputs.json")["path"]))
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if identity.get("status") != "captured":
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raise ValueError("missing successful source capture")
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inputs = b.read_json(b.check_artifact(identity["source"]["inputs"]))
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if any(b.sha256(ROOT / name) != digest for name, digest in inputs.items()):
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raise ValueError("captured source changed")
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flows = {}
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for key in ("snapshot", "patch"):
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b.check_artifact(identity["source"][key])
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for tool in identity["tools"].values():
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b.check_artifact(tool["executable"])
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b.check_artifact(tool["archive"])
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for name in ("syn/yosys/result-synth.json", "sta/opensta/result-sta.json"):
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path = variant / name
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result = b.read_json(path)
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if result.get("status") != "passed" or result.get("exit_code") != 0:
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raise ValueError(f"incomplete flow: {name}")
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if datetime.fromisoformat(result["started_at"]) < datetime.fromisoformat(identity["created_at"]):
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raise ValueError(f"flow predates captured source: {name}")
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flows[name] = b.artifact(path)
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sta = variant / "sta/opensta"
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mapped = variant / "syn/yosys/out/retrosoc_tiny_asic_yosys.v"
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verify_netlist(variant, mapped, mapped.with_suffix(".config"),
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variant / "syn/yosys/tiny-ics55-netlist.json")
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log = (sta / "opensta.log").read_text()
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if "TINY_ICS55_STA_AUDIT_PASS:" not in log or re.search(r"(?im)^Error:|\bFATAL\b|%Error", log):
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raise ValueError("incomplete or erroneous STA audit")
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metrics = timing_metrics(sta / "timing_metrics.rpt")
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report = {"phase": PHASE, "status": "completed", "source": identity,
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"flows": flows, "qualification": "SAFE24 synthesis/STA observation only; functional acceptance is separate",
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"timing": metrics,
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"timing_status": "failed" if any(v < 0 for v in metrics.values()) else "nonnegative_reported_slack",
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"sys_setup_slack_ns": path_slack(sta / "sys-setup.rpt"),
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"sys_hold_slack_ns": path_slack(sta / "sys-hold.rpt"),
|
|
"sta_artifacts": {p.name: b.artifact(p) for p in sta.iterdir() if p.is_file()},
|
|
"macro_audit": b.artifact(variant / "syn/yosys/tiny-ics55-netlist.json")}
|
|
b.dump(parent / "report.json", report)
|
|
print(f"{PHASE} {args.action}: PASS (not physical qualification)")
|
|
return 0
|
|
except (OSError, ValueError, KeyError) as error:
|
|
if args.action == "capture" and "directory" in locals():
|
|
b.dump(directory / "identity.json", {"phase": PHASE, "status": "failed", "error": str(error)})
|
|
print(f"{PHASE}: {error}", file=sys.stderr)
|
|
return 1
|
|
|
|
|
|
if __name__ == "__main__":
|
|
raise SystemExit(main())
|