mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
952b060a70
Integrate RNG, CRC, WS2812, Crypto, I2S master and the SDIO private AXI owner on SAFE24. Preserve the 128 KiB main SRAM and six private Crypto macros, add product-specific DMA assignments and reject unsupported SDK operations.
Correct APB read strobes, I2S receive assembly and SDIO command timing, backpressure and descriptor retirement. Add pin-level workloads, source-bound evidence checks and publication/commercial consumer compatibility.
Validation of the final P6 worktree: 1726 pytest tests passed with one optional pypdf skip (exit 0, 4021.61 seconds; terminal session 36439). Both PDKs passed both RTL simulators, netlist boot and 38-macro binding checks. Shared formal, Mini compatibility and software/source quality gates passed.
Evidence remains attributed to the retained dirty-worktree snapshots based on b3b30a72cd under build/ics55-tiny-2026-10-12-11-50-2eb98c0e1fae/meta/tiny-r2-p6/. Timing is negative and warning observations are not promoted. This commit does not accept P6, qualify physical operation or enable P7.
242 lines
14 KiB
Python
242 lines
14 KiB
Python
#!/usr/bin/env python3
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"""Generate Tiny integration bindings and absolute source lists from owned maps."""
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from __future__ import annotations
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import argparse
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import json
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import re
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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sys.path.insert(0, str(ROOT))
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from scripts.rtl.generate_memory_map import generate as generate_memory_map # noqa: E402
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from scripts.rtl.generate_pin_map import generate as generate_pin_map # noqa: E402
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from scripts.setup_helpers import atomic_write # noqa: E402
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TINY = ROOT / "rtl/tiny"
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def read_topology(path: Path, memory_map: Path) -> dict:
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document = json.loads(path.read_text())
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regions = {r["symbol"] for r in json.loads(memory_map.read_text())["regions"]}
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if (document.get("schema_version") != 1 or document.get("dma_channels") != 8
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or document.get("dma_request_mask") != "0x31ff"):
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raise ValueError("Tiny P6 requires eight DMA channels and request mask 0x31ff")
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if document.get("cpu") != {"module": "hazard3_cpu_2port", "local_ports": 2,
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"data_outstanding": 1}:
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raise ValueError("Tiny P4 requires independent I/D and one ordered data operation")
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memory = document.get("main_sram", {})
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if any(memory.get(key) != value for key, value in {
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"groups": 4, "group_bytes": 32768, "macros_per_group": 8,
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"macro_bytes": 4096, "base": "0x30000000",
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"macro_instance": "u_soc.u_sram.gen_group[{group}].u_group.gen_bank[{bank}].u_ram.u_mem",
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"external_attachment": "per-target-P5",
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}.items()):
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raise ValueError("Tiny SRAM geometry/P5 attachment differs from its frozen contract")
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if document.get("fabric") != {
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"owners": ["cpu_slow", "central_dma", "sdio"], "active_owners": [0, 1, 2],
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"cpu_combined_outstanding": 1, "dma_direction_outstanding": 1,
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"sdio_direction_outstanding": 1, "target_combined_outstanding": 1,
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"sram_targets": [0, 1, 2, 3], "xpi_target": 4, "apb_target_base": 5,
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"decode_error_target": 25, "protocol_error_target": 26, "target_count": 27,
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}:
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raise ValueError("Tiny P6 requires three active owners and 27 targets")
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if document.get("irq_vector_width") != 32 or document.get("external_irq_count") != 30:
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raise ValueError("Tiny requires a 32-bit IRQ vector and 30 external inputs")
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names: set[str] = set()
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bits: set[int] = set()
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for irq in document["interrupts"]:
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if irq["name"] in names or irq["core_bit"] in bits:
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raise ValueError("duplicate Tiny interrupt")
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if not 0 <= irq["core_bit"] < 32:
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raise ValueError("Tiny IRQ outside vector")
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names.add(irq["name"])
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bits.add(irq["core_bit"])
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assigned: set[str] = set()
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for target in document["apb_targets"]:
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for region in target["regions"]:
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if region not in regions or region in assigned:
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raise ValueError(f"invalid or duplicate APB region {region}")
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assigned.add(region)
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if assigned != {r for r in regions if r.startswith("APB4_")}:
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raise ValueError("Tiny topology must route every APB region")
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if len(document["apb_targets"]) != 20:
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raise ValueError("Tiny P6 requires twenty independent APB targets")
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target_names = [target["name"] for target in document["apb_targets"]]
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if len(set(target_names)) != 20 or any(re.fullmatch(r"[a-z][a-z0-9_]*", name) is None
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for name in target_names):
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raise ValueError("Tiny APB target names must be unique identifiers")
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if sorted(item["pin"] for item in document["gpio_alt_functions"]) != list(range(32)):
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raise ValueError("Tiny GPIO map must contain all 32 pins exactly once")
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inputs = [signal for pin in document["gpio_alt_functions"] for mode in ("alt0", "alt1")
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for signal in pin[mode]["inputs"]]
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if len(inputs) != len(set(inputs)):
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raise ValueError("Tiny peripheral inputs require one exclusive route")
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if document.get("private_crypto") != {
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"banks": 6, "bank_bytes": 4096,
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"macro_instance": "u_soc.u_crypto.u_storage.gen_bank[{bank}].gen_macro.u_sram.u_mem",
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"clock_domain": "system", "logical_domain": "PCLK (SAFE24 alias)",
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}:
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raise ValueError("Tiny P6 requires six private Crypto banks on SAFE24 PCLK")
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return document
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def platform_values(pdk: str, have_pll: bool = False) -> dict[str, int]:
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if (pdk, have_pll) not in (("IHP130", False), ("ICS55", True)):
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raise ValueError("unsupported Tiny PDK/PLL combination")
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return {"technology": 0x02040037 if pdk == "ICS55" else 0x02010082,
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"features0": 0x7FFE | int(have_pll), "pll_present": int(have_pll),
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"gpio_pulls": int(pdk == "ICS55")}
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def generate_bindings(document: dict, output: Path, pdk: str = "IHP130",
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have_pll: bool = False) -> None:
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platform = platform_values(pdk, have_pll)
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comment = "// Generated by scripts/generate_tiny.py; do not edit.\n"
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constants = [comment, "`ifndef RETROSOC_TINY__TOPOLOGY_SVH",
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"`define RETROSOC_TINY__TOPOLOGY_SVH",
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f"`define RETROSOC_TINY__TARGET_COUNT {document['fabric']['target_count']}",
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f"`define RETROSOC_TINY__LEAF_COUNT {len(document['apb_targets']) + 1}",
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f"`define RETROSOC_TINY__DECODE_ERROR {document['fabric']['decode_error_target']}",
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f"`define RETROSOC_TINY__PROTOCOL_ERROR {document['fabric']['protocol_error_target']}"]
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constants += [f"`define RETROSOC_TINY__TARGET_{target['name'].upper()} {index + 5}"
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for index, target in enumerate(document["apb_targets"])]
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constants.append("`endif\n")
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atomic_write(output / "rtl/tiny_topology.svh", "\n".join(constants))
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# Keep board pulls independently resolved. A packed tri1 with partial
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# external drivers loses its weak pulls in the locked Verilator 5.046.
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board = [comment, *[f"tri1 s_gpio_{pin};" for pin in range(document["gpio_pins"])]]
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board.append("wire [31:0] s_gpio = {" +
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", ".join(f"s_gpio_{pin}" for pin in reversed(range(32))) + "};\n")
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atomic_write(output / "rtl/tiny_tb_gpio.svh", "\n".join(board))
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irq = [comment, "always_comb begin", " s_irq = '0;"]
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header = ["#ifndef RETROSOC_GENERATED_IRQ_METADATA_H",
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"#define RETROSOC_GENERATED_IRQ_METADATA_H", "#include <stdint.h>",
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"#define RS_SOC_IRQ_VECTOR_WIDTH UINT32_C(32)",
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"#define RS_SOC_EXTERNAL_IRQ_COUNT UINT32_C(30)",
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f"#define RS_SOC_ALLOCATED_IRQ_COUNT UINT32_C({len(document['interrupts']) - 2})"]
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for item in document["interrupts"]:
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bit, name = item["core_bit"], item["name"].upper()
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irq.append(f" s_irq[{bit}] = {item['signal']};")
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header.append(f"#define RS_SOC_IRQ_{name} UINT32_C({bit})")
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if bit >= 2:
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header.append(f"#define RS_SOC_EXT_IRQ_{name} UINT32_C({bit - 2})")
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irq.append("end\n")
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header.append("#endif\n")
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atomic_write(output / "rtl/tiny_irq.svh", "\n".join(irq))
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atomic_write(output / "include/retrosoc/generated/irq_metadata.h", "\n".join(header))
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atomic_write(output / "include/retrosoc/generated/user_extensions.h",
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"#ifndef RETROSOC_GENERATED_USER_EXTENSIONS_H\n"
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"#define RETROSOC_GENERATED_USER_EXTENSIONS_H\n"
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"#define RS_SOC_USER_CORE_COUNT 0U\n#define RS_SOC_USER_IP_COUNT 0U\n"
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"#define RS_SOC_HAS_USER_CORES 0U\n#define RS_SOC_HAS_USER_IP_MUX 0U\n#endif\n")
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atomic_write(output / "include/retrosoc/generated/soc_features.h",
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"#ifndef RETROSOC_GENERATED_SOC_FEATURES_H\n"
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"#define RETROSOC_GENERATED_SOC_FEATURES_H\n"
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"#define RS_SOC_TINY 1\n#define RS_SOC_HAS_PSRAM 0U\n"
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"#define RS_SOC_DMA_CHANNELS 8U\n#define RS_SOC_ID 0x54494E59U\n"
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"#define RS_SOC_DMA_REQUEST_MASK 0x31FFU\n"
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"#define RS_SOC_HAS_I2C1 0U\n#define RS_SOC_HAS_SDIO1 0U\n"
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"#define RS_SOC_HAS_UART0 1U\n#define RS_SOC_HAS_UART1 0U\n"
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"#define RS_SOC_HAS_I2C0 1U\n"
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"#define RS_SOC_HAS_RNG 1U\n#define RS_SOC_HAS_CRC 1U\n"
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"#define RS_SOC_HAS_WS2812 1U\n#define RS_SOC_HAS_CRYPTO 1U\n"
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"#define RS_SOC_HAS_I2S 1U\n#define RS_SOC_HAS_SDIO0 1U\n"
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"#define RS_SOC_HAS_DVP 0U\n#define RS_SOC_RNG_QUALIFIED 0U\n"
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f"#define RS_SOC_TECHNOLOGY_ID 0x{platform['technology']:08X}U\n"
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f"#define RS_SOC_PLL_PRESENT {platform['pll_present']}U\n"
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f"#define RS_SOC_GPIO_HAS_PULLS {platform['gpio_pulls']}U\n#endif\n")
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atomic_write(output / "rtl/tiny_platform.svh", comment +
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f"`define RETROSOC_TINY__TECHNOLOGY 32'h{platform['technology']:08x}\n"
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f"`define RETROSOC_TINY__FEATURES0 32'h{platform['features0']:08x}\n")
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gpio = [comment]
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for function in document["gpio_alt_functions"]:
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pin = function["pin"]
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for mode in ("alt0", "alt1"):
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value = function[mode]
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gpio.extend(f"assign {signal} = u_gpio_if.di_i[{pin}];" for signal in value["inputs"])
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gpio.extend((f"assign u_gpio_if.{mode}_do_i[{pin}] = {value['do']};",
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f"assign u_gpio_if.{mode}_oe_i[{pin}] = {value['oe']};"))
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atomic_write(output / "rtl/tiny_gpio.svh", "\n".join(gpio) + "\n")
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declarations, bridges, decode = [comment], [comment], [comment]
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reset_assignments = []
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for index, target in enumerate(document["apb_targets"]):
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name = target["name"]
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declarations.append(f"logic s_{name}_rst_n;")
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declarations.append(f"apb4_if u_{name}_apb4_if (.pclk(clk_i), .presetn(s_{name}_rst_n));")
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reset_assignments.append(f"assign s_{name}_rst_n = s_leaf_rst_n[{index + 1}];")
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bridges.append(f"assign s_target_rst_n[{index + 5}] = s_{name}_rst_n;")
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bridges.append(f"tiny_axi42apb4 u_{name}_bridge ("
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f".clk_i(clk_i), .rst_n_i(s_{name}_rst_n), "
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f".axi4(u_targets_axi4_if[{index + 5}]), .apb4(u_{name}_apb4_if));")
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decode.append(f"if ({' || '.join(f'`SOC_ADDR_IS_{r}(addr_i)' for r in target['regions'])}) "
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f"return 5'd{index + 5};")
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atomic_write(output / "rtl/tiny_apb_interfaces.svh", "\n".join(declarations + reset_assignments) + "\n")
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atomic_write(output / "rtl/tiny_apb_bridges.svh", "\n".join(bridges) + "\n")
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atomic_write(output / "rtl/tiny_fabric_decode.svh", "\n".join(decode) + "\n")
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def generate_filelists(output: Path, generated: Path, defines: list[str],
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pdk: str = "IHP130", simulator: str = "VERILATOR",
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synthesis: str = "NONE") -> None:
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prefixes = {"top": TINY / "top", "dv": TINY / "dv", "ip": ROOT / "rtl/ip",
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"tech": ROOT / "rtl/tech", "clusterip": ROOT / "rtl/managed/clusterip",
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"hazard3": ROOT / "rtl/managed/hazard3/hdl", "physical": ROOT / "physical",
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"cache": ROOT / ".cache", "tests": ROOT / "tests"}
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suffix = "_yosys" if synthesis == "YOSYS" else "_verilator" if simulator == "VERILATOR" else ""
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pdk_name = "pdk_ihp130.fl" if pdk == "IHP130" else f"pdk_ics55{suffix}.fl"
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templates = [*sorted((TINY / "filelist").glob("*.fl")),
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ROOT / "rtl/filelist" / pdk_name]
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for template in templates:
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content = template.read_text()
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for prefix, directory in prefixes.items():
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content = re.sub(rf"(?<![^\s+])/{prefix}(?=/|\s|$)", str(directory), content)
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if template.name == pdk_name and pdk == "ICS55":
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# The shared tc_sram file also declares an unused 16 KiB wrapper.
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# Keep its official interface visible to parsers; Tiny must never
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# instantiate it (the mapped-netlist audit rejects that case).
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content = content.replace("ics55_ecos_sram_4096x32_m8_core.v",
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"ics55_ecos_sram_4096x32_m8_stub.v")
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atomic_write(output / template.name, content)
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if template.name == pdk_name:
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if pdk == "ICS55" and synthesis != "YOSYS":
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content += str(ROOT / ".cache/retrosoc/sources/ics55_ecos_pll/verilog/PLL_TOP.behavioral.v") + "\n"
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atomic_write(output / "pdk_selected.fl", content)
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include = [TINY / "dv", generated / "rtl", generated / "memory_map/rtl", generated / "pin_map/rtl",
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generated / "archinfo"]
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atomic_write(output / "def.fl", " ".join([*defines, *(f"+incdir+{p}" for p in include)]) + "\n")
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atomic_write(output / "pdk_local.fl", "")
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def main() -> int:
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parser = argparse.ArgumentParser(description=__doc__)
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parser.add_argument("--output", type=Path)
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parser.add_argument("--filelists", type=Path)
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parser.add_argument("--define", action="append", default=[])
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parser.add_argument("--check", action="store_true")
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parser.add_argument("--pdk", choices=("IHP130", "ICS55"), default="IHP130")
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parser.add_argument("--simulator", choices=("IVERILOG", "VERILATOR"), default="VERILATOR")
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parser.add_argument("--synthesis", choices=("NONE", "YOSYS"), default="NONE")
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args = parser.parse_args()
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document = read_topology(TINY / "integration/soc_topology.json",
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TINY / "address_map/memory_map.json")
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if args.check:
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return 0
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if args.output is None or args.filelists is None:
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parser.error("--output and --filelists are required unless --check is used")
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if any(not value.startswith("+define+") for value in args.define):
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parser.error("--define requires a +define+ token")
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output = args.output.resolve()
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generate_memory_map(TINY / "address_map/memory_map.json", output / "memory_map", "YES", 128)
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generate_pin_map(TINY / "pin_map/pin_map.json", output / "pin_map", read_while_driving=True)
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generate_bindings(document, output, args.pdk, "+define+HAVE_PLL" in args.define)
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generate_filelists(args.filelists.resolve(), output, args.define,
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args.pdk, args.simulator, args.synthesis)
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return 0
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if __name__ == "__main__":
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raise SystemExit(main())
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