mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
91 lines
4.2 KiB
Python
91 lines
4.2 KiB
Python
"""Dense overview labels and fan-in must stay tied to current PRODUCT sources."""
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from __future__ import annotations
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import copy
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import json
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from pathlib import Path
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import pytest
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from publications.soc_diagram_reference import validate_soc_diagram
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ROOT = Path(__file__).resolve().parents[1]
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@pytest.fixture
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def diagram():
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return json.loads((ROOT / "publications/datasheets/soc-architecture.json").read_text(encoding="utf-8"))
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def test_dense_overview_retains_instances_and_independent_gateway_fan_in(diagram):
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validate_soc_diagram(ROOT, diagram)
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assert diagram["font_weight"] == 400
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assert [len(gateway["members"]) for gateway in diagram["gateways"]] == [3, 2]
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assert len(diagram["masters"]) == 10
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nodes = {node["id"]: node for node in diagram["nodes"]}
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assert nodes["sram"]["domain"] == nodes["monitor"]["domain"] == "hp"
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assert nodes["gwa"]["domain"] == nodes["gwb"]["domain"] == "pclk"
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assert {nodes[id]["domain"] for id in ["sdram", "qpi", "opi", "xpi"]} == {"memory"}
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assert diagram["pclk_parent"] == "lp"
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@pytest.mark.parametrize("mutation", ["bold", "small-font", "compact-ip", "compact-weight", "arrow-size", "module-width-label", "wire-width-label",
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"gateway-input", "gateway-output", "gateway-source", "bridge-width",
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"printed-width", "bus-width", "clock-domain", "clock-pin", "clock-parent",
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"interface-source", "interface-token", "interface-af", "interface-bus",
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"ip-coverage", "instance-coverage", "stream-source", "missing-source"])
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def test_overview_rejects_visual_claims_that_contradict_its_scope_or_sources(diagram, mutation):
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nodes = {node["id"]: node for node in diagram["nodes"]}
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if mutation == "bold":
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diagram["font_weight"] = 700
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elif mutation == "small-font":
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diagram["font_size_pt"] = 8
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elif mutation == "compact-ip":
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nodes["dma"]["compact"] = True
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elif mutation == "compact-weight":
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diagram["typography"]["emphasis_weight"] = 600
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elif mutation == "arrow-size":
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diagram["routing"]["arrow_length_mm"] = 2
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elif mutation == "module-width-label":
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nodes["dma"]["label"] += " AXI32"
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elif mutation == "wire-width-label":
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diagram["edges"][0]["label"] = "AXI64"
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elif mutation == "gateway-input":
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diagram["edges"] = [edge for edge in diagram["edges"] if not (edge["from"] == "apu" and edge["to"] == "gwa")]
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elif mutation == "gateway-output":
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edge = copy.deepcopy(next(edge for edge in diagram["edges"] if edge["from"] == "gwa"))
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edge["to"] = "hp_bus"
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diagram["edges"].append(edge)
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elif mutation == "gateway-source":
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diagram["gateways"][0]["members"]["icache"]["signal"] = "jpeg_axi4"
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elif mutation == "bridge-width":
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diagram["bridges"][0]["input_bits"] = 32
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elif mutation == "printed-width":
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nodes["gca"]["label"] = "AXI64→AXI32 / CDC"
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elif mutation == "bus-width":
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nodes["hp_bus"]["label"] = "HP data interconnect · AXI32"
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elif mutation == "clock-domain":
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nodes["sram"]["domain"] = "pclk"
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elif mutation == "clock-pin":
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nodes["sram"]["clock"]["signal"] = "clk_lp_i"
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elif mutation == "clock-parent":
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diagram["pclk_parent"] = "hp"
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elif mutation == "interface-source":
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diagram["interfaces"][0]["source"] = "missing.sv"
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elif mutation == "interface-token":
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diagram["interfaces"][0]["tokens"] = ["nonexistent_pin"]
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elif mutation == "interface-af":
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next(row for row in diagram["interfaces"] if "af_prefix" in row)["af_prefix"] = "u_nonexistent_if."
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elif mutation == "interface-bus":
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next(row for row in diagram["interfaces"] if "pin_bus" in row)["pin_bus"]["count"] += 1
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elif mutation == "ip-coverage":
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nodes["crypto"]["ips"] = []
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elif mutation == "instance-coverage":
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nodes["i2c1"]["id"] = "merged-i2c"
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elif mutation == "stream-source":
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diagram["stream_bindings"][0]["ports"]["i2s_tx_axis"] = "wrong_stream"
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else:
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diagram["sources"].remove("rtl/mini/pin_map/pin_map.json")
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with pytest.raises(ValueError, match="SoC diagram"):
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validate_soc_diagram(ROOT, diagram)
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