mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
bc48cec74a
Integrate the Tiny RCU, normalized REF24 control, external-input profiles, single PLL backend, SYS/MEM/PCLK clocks, CPU-only WFI gating, peripheral lifecycle control and retained debug behavior. Keep CPU and all 32 main SRAM macros on SYS and the six private Crypto macros on PCLK. Add the handwritten RCU register/HAL contract, RS_EBUSY, bounded SDK operations and focused firmware. Preserve shared-IP defaults and the ICS55/PLL SAFE24 boot and explicit IHP130/no-PLL compatibility profiles. Use APB/AXI domain bridges and source-owned response holders to preserve backpressured responses, complete aborted bursts and prevent stale replay. Verify production DMA source-reset drain and common XPI endpoint reset with extracted integration bindings and an independent scoreboard. Add source-bound macro/clock audits, SAFE24 observational STA constraints and commercial-adapter host checks. No P8 functionality or operating-point qualification is included. See TINY-R2-P7 in docs/ip/tiny-soc.md. Validation: 54 P7 directed tests pass, including both simulators, ten source-reset ratio runs and two expected-negative drain mutations. RTL format/style, clock/reset inventory, Ruff and both Tiny PDK PR dry-runs pass. Retained 06-00 synthesis and strict netlist boots pass for both PDKs; STA remains negative and observational. Source comparison confirms only the follow-up tests changed after that backend campaign. Evidence: build/ics55-tiny-2026-10-14-06-00-ff4b5cef6eb5/meta/ tiny-r2-p7-source-reset/summary.json. Earlier firmware, HAL and compatibility results and the non-clean full-suite attempt retain their original attribution. Full Icarus firmware is deferred to final Tiny qualification; this commit does not constitute human phase acceptance or physical signoff.
194 lines
10 KiB
Python
194 lines
10 KiB
Python
"""P5 target concurrency, fault accounting and retained-image acceptance."""
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from __future__ import annotations
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import shutil
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import subprocess
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import json
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from pathlib import Path
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import pytest
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from scripts.generate_tiny import generate_bindings, generate_filelists, read_topology
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from scripts.rtl.filelist import parse_filelists
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from scripts.rtl.generate_memory_map import generate as generate_memory_map
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from test_tiny_r2_p4 import run
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from scripts import tiny_r2_p5 as p5
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ROOT = Path(__file__).resolve().parents[1]
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COMMON = ROOT / "rtl/managed/clusterip/common/rtl"
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TINY = ROOT / "rtl/tiny/top"
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def sources(tmp_path):
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generate_memory_map(ROOT / "rtl/tiny/address_map/memory_map.json", tmp_path / "map", "YES", 128)
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generate_bindings(read_topology(ROOT / "rtl/tiny/integration/soc_topology.json",
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ROOT / "rtl/tiny/address_map/memory_map.json"), tmp_path / "bindings")
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files = [COMMON / p for p in ("utils/register.sv", "utils/spill_register.sv",
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"utils/fifo.sv", "stream/round_robin_arbiter.sv", "interface/axi4_if.sv",
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"interface/axi4_addr_gen.sv", "interface/apb4_if.sv", "interface/ahbl_if.sv")]
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files += [TINY / p for p in ("tiny_axi4_target.sv", "tiny_axi4_fabric.sv",
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"tiny_axi42apb4.sv", "tiny_fault_collector.sv", "tiny_sysctrl.sv")]
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files += [ROOT / "rtl/ip/interconnect/axi4_error_slave.sv"]
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includes = [f"-I{p}" for p in (COMMON, COMMON / "interface", TINY, tmp_path / "map/rtl",
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tmp_path / "bindings/rtl", ROOT / "rtl/ip/peripheral", ROOT / "tests/rtl")]
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return files, includes
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def simulate(tmp_path, simulator, top, files, includes, arguments=()):
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for tool in (simulator, "sv2v", "vvp"):
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assert shutil.which(tool), f"required tool unavailable: {tool}"
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binary = tmp_path / "sim"
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if simulator == "verilator":
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run([simulator, "--binary", "--timing", "--assert", "-Wno-fatal", "-j", "3",
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"-DHAVE_SVA", "-DSV_ASSRT_DISABLE", "--top-module", top, *includes,
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*(str(p) for p in files), "--Mdir", str(tmp_path / "obj"), "-o", str(binary)],
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tmp_path, "compile", timeout=300)
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launch = [str(binary)]
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else:
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# Conversion warnings are diagnostics, never Verilog source text.
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converted = subprocess.run(["sv2v", "-DSV_ASSRT_DISABLE", *includes,
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*(str(p) for p in files)], text=True,
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capture_output=True, timeout=300)
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(tmp_path / "sv2v.log").write_text(converted.stderr)
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assert converted.returncode == 0, converted.stderr
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(tmp_path / "converted.v").write_text(converted.stdout)
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run([simulator, "-g2012", "-s", top, "-o", str(binary), str(tmp_path / "converted.v")],
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tmp_path, "compile")
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launch = ["vvp", str(binary)]
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log = run([*launch, *arguments], tmp_path, "sim", timeout=180)
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assert "SIM_TEST_PASS Tiny P5" in log
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return log
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@pytest.mark.parametrize("simulator", ["iverilog", "verilator"])
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def test_concurrent_fabric(tmp_path, simulator):
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files, includes = sources(tmp_path)
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files.append(ROOT / "tests/rtl/tiny_r2_p5_fabric_tb.sv")
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log = simulate(tmp_path, simulator, "tiny_r2_p5_fabric_tb", files, includes)
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assert "random_reads=96 concurrent_faults=2" in log
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@pytest.mark.parametrize("simulator", ["iverilog", "verilator"])
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def test_target_reset_isolation(tmp_path, simulator):
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files, includes = sources(tmp_path)
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files.append(ROOT / "rtl/ip/peripheral/dma_axi4_master.sv")
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files.append(ROOT / "tests/rtl/tiny_r2_p5_reset_tb.sv")
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log = simulate(tmp_path, simulator, "tiny_r2_p5_reset_tb", files, includes)
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assert "SIM_TEST_PASS Tiny P5 target reset isolation" in log
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assert "P5_RESET cases=28 production_dma=3 burst_beats=16 held_RB=1 first_fault=1" in log
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@pytest.mark.parametrize("simulator", ["iverilog", "verilator"])
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def test_real_cpu_dma_progress_and_abort(tmp_path, simulator):
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sources(tmp_path)
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firmware = tmp_path / "cpu.elf"
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run(["riscv32-unknown-elf-gcc", "-march=rv32imc_zicsr_zifencei", "-mabi=ilp32",
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"-nostdlib", "-Wl,--build-id=none", "-T", str(ROOT / "tests/rtl/tiny_r2_p4_cpu.ld"),
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str(ROOT / "tests/rtl/tiny_r2_p5_cpu.S"), "-o", str(firmware)], tmp_path, "firmware")
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run(["riscv32-unknown-elf-objcopy", "-O", "verilog", str(firmware), str(tmp_path / "cpu.hex")],
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tmp_path, "objcopy")
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generate_filelists(tmp_path / "filelists", tmp_path / "bindings", [])
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resolved = parse_filelists(tmp_path / "filelists" / name for name in (
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"inc.fl", "commonip.fl", "clusterip.fl", "core_hazard3.fl", "ip.fl", "tech.fl", "top.fl"))
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# Only the XPI boundary is substituted; the production CPU/DMA/SoC stay real.
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files = [p for p in resolved.files if p.name not in ("apb4_xpi.sv", "retrosoc_tiny_asic.sv")]
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files.append(ROOT / "tests/rtl/tiny_r2_p5_system_tb.sv")
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run(["python3", str(ROOT / "rtl/managed/clusterip/archinfo/scripts/generate_metadata.py"),
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"--repo-root", str(ROOT), "--lock", str(ROOT / "dependencies/dependencies.lock.json"),
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"--config-digest", "000000000000", "--output-sv", str(tmp_path / "archinfo_integration_metadata.svh"),
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"--output-c", str(tmp_path / "archinfo_integration_metadata.h")], tmp_path, "metadata")
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includes = [f"-I{p}" for p in (*resolved.incdirs, tmp_path, tmp_path / "map/rtl",
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tmp_path / "bindings/rtl", ROOT / "rtl/tiny/dv")]
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includes += ["-DPDK_BEHAV", "-DRETROSOC_SOC__TINY", "-DSOC_JTAG_IDCODE=32'hDEADBEEF",
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"-DSOC_EXT_CLK_HZ=24000000"]
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log = simulate(tmp_path, simulator, "tiny_r2_p5_system_tb", files, includes,
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[f"+firmware={tmp_path / 'cpu.hex'}"])
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assert "hart_reset=1 abort_drained=1" in log
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@pytest.mark.parametrize("kind", ["fabric", "fabric_reset", "fault"])
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def test_protocol_proofs(tmp_path, kind):
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for tool in ("sv2v", "yosys"):
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assert shutil.which(tool), f"required tool unavailable: {tool}"
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files, includes = sources(tmp_path)
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top = f"tiny_r2_p5_{'fabric' if kind == 'fabric_reset' else kind}_formal"
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files.append(ROOT / f"tests/rtl/{top}.sv")
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reset_define = ["-DTINY_P5_RESET_FORMAL"] if kind == "fabric_reset" else []
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converted = subprocess.run(["sv2v", "-DFORMAL", "-DSV_ASSRT_DISABLE", *reset_define, *includes,
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*(str(p) for p in files)], text=True, capture_output=True, timeout=180)
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(tmp_path / "sv2v.log").write_text(converted.stderr)
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assert converted.returncode == 0, converted.stderr
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(tmp_path / "formal.v").write_text(converted.stdout)
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proof = "sat -prove-asserts -verify" if kind == "fault" else (
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"sat -seq 12 -tempinduct -prove-asserts -verify -set-init-zero")
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script = (f"read_verilog -formal {tmp_path / 'formal.v'}; prep -top {top} -flatten; "
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f"memory_map; async2sync; dffunmap; opt; {proof}")
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log = run(["yosys", "-p", script], tmp_path, "formal", timeout=300)
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assert "SUCCESS!" in log
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def p5_log():
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from test_tiny_r2_p4 import p4_log
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return p4_log() + "\n" + "\n".join(
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f"R2_P5_FABRIC window={window} active_targets_max=3 "
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"dma_rw_overlap_cycles=5 dma_rw_beat_overlap_cycles=2" for window in range(1, 9))
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def test_p5_records_keep_old_image_measurements_separate():
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samples = p5.parse_log(p5_log(), {"status": "passed", "exit_code": 0})
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assert len(samples["fabric"]) == 8
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assert len(samples["local"]) == 16
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assert p5.PHASE == "TINY-R2-P5" and p5.previous.PHASE == "TINY-R2-P4"
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@pytest.mark.parametrize("mutation", ["missing", "duplicate", "negative", "overflow", "overlap", "serialized", "failure"])
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def test_p5_rejects_invalid_concurrency_evidence(mutation):
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content = p5_log()
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if mutation == "missing":
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content = "\n".join(line for line in content.splitlines() if not line.startswith("R2_P5_FABRIC window=8"))
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elif mutation == "duplicate":
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content += "\n" + content.splitlines()[-1]
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elif mutation == "negative":
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content = content.replace("active_targets_max=3", "active_targets_max=-1")
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elif mutation == "overflow":
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content = content.replace("active_targets_max=3", "active_targets_max=24")
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elif mutation == "overlap":
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content = content.replace("dma_rw_beat_overlap_cycles=2", "dma_rw_beat_overlap_cycles=6")
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elif mutation == "serialized":
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content = content.replace("active_targets_max=3", "active_targets_max=1")
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else:
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content += "\nSIM_TEST_FAIL"
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with pytest.raises(ValueError):
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p5.parse_log(content, {"status": "passed", "exit_code": 0})
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@pytest.mark.parametrize("mutation", ["none", "phase", "source", "cycles", "image", "local"])
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def test_p5_reference_is_bound_to_p4_execution(tmp_path, monkeypatch, mutation):
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case = {"name": "flat", "image": {"path": "immutable"},
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"samples": {"cases": [{"name": "dma16", "cycles": 17897, "instructions": 10}],
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"local": [], "banks": []}}
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report = {"phase": "TINY-R2-P4", "status": "measurement_complete", "source_digest": "original",
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"executions": {"verilator": {}}, "comparisons": [
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{"name": "flat", "image": {"path": "immutable"}, "local": [], "banks": [],
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"workloads": [{"name": "dma16", "candidate_cycles": 17897, "candidate_instructions": 10}]}]}
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monkeypatch.setattr(p5.previous, "validate_replay", lambda *args: {
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"source_digest": "original", "cases": [case]})
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monkeypatch.setattr(p5.b, "check_artifact", lambda artifact: tmp_path / "record.json")
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if mutation == "phase":
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report["phase"] = "TINY-R2-P5"
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elif mutation == "source":
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report["source_digest"] = "other"
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elif mutation == "cycles":
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report["comparisons"][0]["workloads"][0]["candidate_cycles"] = 1
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elif mutation == "image":
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report["comparisons"][0]["image"]["path"] = "different"
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elif mutation == "local":
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report["comparisons"][0]["local"] = [{}]
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path = tmp_path / "report.json"
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path.write_text(json.dumps(report))
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if mutation == "none":
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assert p5.reference_cases(path, ["flat"]) == [case]
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else:
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with pytest.raises(ValueError):
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p5.reference_cases(path, ["flat"])
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