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maksyuki
7418acfe42
- Adjusted variable alignment in Makefiles for better readability. - Ensured consistent formatting across various Makefiles and scripts. - Added a new .bake.toml file to define project formatting policies for mbake. - Updated paths and variable definitions in multiple configuration files to enhance clarity. - Removed unnecessary comments and whitespace for cleaner code.
RTL Design and Simulation
This directory contains retroSoC SystemVerilog RTL, CPU/IP integration, peripheral and technology wrappers, filelists, testbench support, and the Mini SoC build entry points.
mini/ is the active SoC integration flow. managed/ contains locked or
vendored integration inputs, while ip/ contains self-owned IP and
experiments. filelist/ selects PDK-specific RTL sources; tech/ contains
technology wrappers. Respect managed upstream boundaries and use setup helpers
rather than editing generated MPW output.
RTL changes require an affected firmware build and simulation. Use
make regress-pr or make regress-nightly for supported regression coverage;
see Engineering Workflow for results and artifacts.