mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
7592808464
- Updated the JPEG table register bank module to use combinational logic for data handling and simplified the write logic for quantization, DC, and AC entries. - Introduced a new function in the run_flow script to handle process termination more gracefully, including signal handling for interrupts. - Enhanced the flow script to log peak RSS memory usage during execution. - Modified multiple testbench files to include new storage access signals and improved the test logic for better validation of KWS and SRAM interactions. - Updated tests to validate the new peak RSS memory logging in the flow script. - Adjusted Yosys synthesis recipes to include timeout settings and ensure proper reporting of pre-memory synthesis outputs.
83 lines
3.2 KiB
Makefile
83 lines
3.2 KiB
Makefile
# Copyright (c) 2022 ETH Zurich and University of Bologna.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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#
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# Authors:
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# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
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#
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# -- Adaptable modifications are redistributed under compatible License --
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#
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# Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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# retroSoC is licensed under Mulan PSL v2.
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# You can use this software according to the terms and conditions of the Mulan PSL v2.
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# You may obtain a copy of Mulan PSL v2 at:
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# http://license.coscl.org.cn/MulanPSL2
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# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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# See the Mulan PSL v2 for more details.
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# Directories
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# directory of the path to the last called Makefile (this one)
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YOSYS_DIR := $(realpath $(dir $(realpath $(lastword $(MAKEFILE_LIST)))))
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YOSYS_BUILD := $(SYN_BUILD_ROOT)
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YOSYS_OUT := $(YOSYS_BUILD)/out
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YOSYS_TMP := $(YOSYS_BUILD)/tmp
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YOSYS_RPT := $(YOSYS_BUILD)/rpt
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YOSYS_TIMEOUT ?= 10800
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include $(YOSYS_DIR)/synth_config.mk
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ifeq ($(origin YOSYS_TARGET_PERIOD_PS),undefined)
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YOSYS_TARGET_PERIOD_PS := $(shell python3 $(ROOT_PATH)/scripts/yosys_period.py \
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--domains $(ROOT_PATH)/rtl/mini/integration/clock_reset_domains.json)
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ifeq ($(strip $(YOSYS_TARGET_PERIOD_PS)),)
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$(error Failed to derive YOSYS_TARGET_PERIOD_PS from the clock/reset inventory)
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endif
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endif
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TOP_DESIGN ?= retrosoc_asic
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RTL_NAME ?= retrosoc_asic
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SV_FLIST := $(GENERATED_FL_DIR)/yosys.fl
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NETLIST := $(YOSYS_OUT)/$(RTL_NAME)_yosys.v
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NETLIST_DEBUG := $(YOSYS_OUT)/$(RTL_NAME)_yosys_debug.v
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NETLIST_CONFIG := $(YOSYS_OUT)/$(RTL_NAME)_yosys.config
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YOSYS_DEPFILE := $(YOSYS_BUILD)/yosys.d
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YOSYS_SCRIPTS := $(wildcard $(YOSYS_DIR)/script/*) $(YOSYS_DIR)/synth_config.mk $(YOSYS_DIR)/yosys.mk
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-include $(YOSYS_DEPFILE)
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$(SV_FLIST): $(MPW_VARIANT_STAMP) $(FILELIST_STAMP)
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@python3 $(RTL_PATH)/script/comb.py $(RTL_FLIST) --output $(SV_FLIST)
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@python3 $(RTL_PATH)/script/filelist_deps.py $(RTL_FLIST) --target $(NETLIST) \
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--output $(YOSYS_DEPFILE)
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gen_synth_filelist: $(SV_FLIST)
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## Synthesize netlist using Yosys
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synth: $(NETLIST) | manifest
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$(NETLIST): $(SV_FLIST) $(YOSYS_SCRIPTS)
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@mkdir -p $(YOSYS_OUT)
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@mkdir -p $(YOSYS_TMP)
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@mkdir -p $(YOSYS_RPT)
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool yosys \
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--log $(YOSYS_BUILD)/$(RTL_NAME).log --result $(YOSYS_BUILD)/result-synth.json \
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--env PDK=$(PDK) --env SOC=$(SOC) --env SYNTH_RECIPE=$(SYNTH_RECIPE) \
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--env HAVE_SRAM_MACRO=$(HAVE_SRAM_MACRO) --env SRAM_SIZE_KIB=$(SRAM_SIZE_KIB) \
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--env YOSYS_TARGET_PERIOD_PS=$(YOSYS_TARGET_PERIOD_PS) \
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--env SV_FLIST=$(SV_FLIST) --env TOP_DESIGN=$(TOP_DESIGN) --env CONFIG=$(NETLIST_CONFIG) \
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--env PROJ_NAME=$(RTL_NAME) --env WORK=$(YOSYS_TMP) --env BUILD=$(YOSYS_OUT) \
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--env REPORTS=$(YOSYS_RPT) --env NETLIST=$(NETLIST) -- \
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timeout --foreground --kill-after=5s $(YOSYS_TIMEOUT)s \
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yosys -t --perffile $(YOSYS_BUILD)/yosys-perf.json -c $(YOSYS_DIR)/script/synth.tcl
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$(NETLIST_DEBUG): $(NETLIST)
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@test -f $@
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synth_clean:
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python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(YOSYS_BUILD)
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.PHONY: gen_synth_filelist synth_clean synth
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