mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
7592808464
- Updated the JPEG table register bank module to use combinational logic for data handling and simplified the write logic for quantization, DC, and AC entries. - Introduced a new function in the run_flow script to handle process termination more gracefully, including signal handling for interrupts. - Enhanced the flow script to log peak RSS memory usage during execution. - Modified multiple testbench files to include new storage access signals and improved the test logic for better validation of KWS and SRAM interactions. - Updated tests to validate the new peak RSS memory logging in the flow script. - Adjusted Yosys synthesis recipes to include timeout settings and ensure proper reporting of pre-memory synthesis outputs.
104 lines
2.9 KiB
Systemverilog
104 lines
2.9 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND.
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module jpeg_table_register_bank (
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// verilog_format: off -- preserve streamed entry and expanded table columns
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input logic clk_i,
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input logic write_i,
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input logic [ 3:0] entry_kind_i,
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input logic [ 7:0] entry_index_i,
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input logic [ 31:0] entry_data_i,
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input logic [ 24:0] entry_reciprocal_i,
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output logic [511:0] quant_o,
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output logic [1599:0] reciprocal_o,
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output logic [191:0] dc_code_o,
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output logic [ 59:0] dc_length_o,
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output logic [4095:0] ac_code_o,
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output logic [1279:0] ac_length_o
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// verilog_format: on
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);
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logic [ 511:0] s_quant_d;
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logic [1599:0] s_reciprocal_d;
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logic [ 191:0] s_dc_code_d;
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logic [ 59:0] s_dc_len_d;
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logic [4095:0] s_ac_code_d;
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logic [1279:0] s_ac_len_d;
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logic s_quant_write, s_dc_write, s_ac_write;
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assign s_quant_write = write_i && (entry_kind_i < 4'd4) && (entry_index_i < 8'd64);
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assign s_dc_write = write_i && (entry_kind_i >= 4'd4) && (entry_kind_i < 4'd8) &&
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(entry_index_i < 8'd12);
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assign s_ac_write = write_i && (entry_kind_i >= 4'd8);
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always_comb begin
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s_quant_d = quant_o;
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s_reciprocal_d = reciprocal_o;
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s_dc_code_d = dc_code_o;
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s_dc_len_d = dc_length_o;
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s_ac_code_d = ac_code_o;
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s_ac_len_d = ac_length_o;
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if (s_quant_write) begin
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s_quant_d[entry_index_i*8+:8] = entry_data_i[7:0];
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s_reciprocal_d[entry_index_i*25+:25] = entry_reciprocal_i;
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end
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if (s_dc_write) begin
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s_dc_code_d[entry_index_i*16+:16] = entry_data_i[15:0];
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s_dc_len_d[entry_index_i*5+:5] = entry_data_i[20:16];
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end
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if (s_ac_write) begin
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s_ac_code_d[entry_index_i*16+:16] = entry_data_i[15:0];
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s_ac_len_d[entry_index_i*5+:5] = entry_data_i[20:16];
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end
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end
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dffl #(
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.DATA_WIDTH(512)
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) u_quant_dffl (
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.clk_i(clk_i),
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.en_i (s_quant_write),
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.dat_i(s_quant_d),
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.dat_o(quant_o)
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);
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dffl #(
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.DATA_WIDTH(1600)
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) u_reciprocal_dffl (
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.clk_i(clk_i),
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.en_i (s_quant_write),
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.dat_i(s_reciprocal_d),
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.dat_o(reciprocal_o)
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);
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dffl #(
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.DATA_WIDTH(192)
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) u_dc_code_dffl (
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.clk_i(clk_i),
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.en_i (s_dc_write),
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.dat_i(s_dc_code_d),
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.dat_o(dc_code_o)
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);
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dffl #(
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.DATA_WIDTH(60)
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) u_dc_length_dffl (
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.clk_i(clk_i),
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.en_i (s_dc_write),
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.dat_i(s_dc_len_d),
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.dat_o(dc_length_o)
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);
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dffl #(
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.DATA_WIDTH(4096)
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) u_ac_code_dffl (
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.clk_i(clk_i),
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.en_i (s_ac_write),
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.dat_i(s_ac_code_d),
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.dat_o(ac_code_o)
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);
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dffl #(
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.DATA_WIDTH(1280)
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) u_ac_length_dffl (
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.clk_i(clk_i),
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.en_i (s_ac_write),
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.dat_i(s_ac_len_d),
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.dat_o(ac_length_o)
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);
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endmodule
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