mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
7592808464
- Updated the JPEG table register bank module to use combinational logic for data handling and simplified the write logic for quantization, DC, and AC entries. - Introduced a new function in the run_flow script to handle process termination more gracefully, including signal handling for interrupts. - Enhanced the flow script to log peak RSS memory usage during execution. - Modified multiple testbench files to include new storage access signals and improved the test logic for better validation of KWS and SRAM interactions. - Updated tests to validate the new peak RSS memory logging in the flow script. - Adjusted Yosys synthesis recipes to include timeout settings and ensure proper reporting of pre-memory synthesis outputs.
542 lines
21 KiB
Systemverilog
542 lines
21 KiB
Systemverilog
`timescale 1ns / 1ps
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module apu_kws_engine_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic enable_i = 1'b0;
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logic counter_clear_i = 1'b0;
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logic xrun_clear_i = 1'b0;
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logic disable_i = 1'b0;
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logic flush_busy_i = 1'b0;
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logic [31:0] status_o, result_o, frame_count_o, inference_count_o, hit_count_o, overrun_count_o;
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logic [31:0] timestamp_lo_o, timestamp_hi_o, model_status_o, model_actual_crc_o;
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logic memory_start_ready_o;
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logic memory_dma_request_valid_o, memory_dma_ready_o, memory_done_o, memory_error_o;
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logic [31:0] memory_input_used_o;
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logic memory_window = 1'b0;
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logic memory_start = 1'b0;
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logic memory_dma_request_ready = 1'b0;
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logic [31:0] memory_dma_data = 32'd0;
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logic [ 3:0] memory_dma_keep = 4'd0;
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logic memory_dma_last = 1'b0;
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logic memory_dma_valid = 1'b0;
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logic memory_dma_done = 1'b0;
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logic memory_dma_error = 1'b0;
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logic [ 5:0] memory_dma_error_code = 6'd0;
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logic [ 3:0] memory_dma_error_stage = 4'd0;
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logic [ 1:0] memory_dma_error_resp = 2'd0;
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logic [31:0] memory_dma_error_address = 32'd0;
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logic [31:0] memory_dma_request_address_o, memory_dma_request_bytes_o;
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logic [5:0] memory_error_code_o;
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logic [3:0] memory_error_stage_o;
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logic [1:0] memory_error_resp_o;
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logic [31:0] memory_error_address_o, memory_error_detail_o;
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logic [10:0] irq_set_o;
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logic fault_valid_o, model_valid_o, model_lock_o, busy_o, idle_o, rx_ready_o;
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logic [5:0] fault_code_o;
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logic [3:0] fault_stage_o;
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logic [1:0] fault_resp_o;
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logic [7:0] fault_index_o;
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logic [31:0] fault_addr_o, fault_detail_o;
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logic [15:0][14:0] model_addr_o;
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logic [15:0][7:0] model_data_i, model_store_data;
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logic storage_req, storage_ready, storage_done, storage_progress, storage_write;
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logic [15:0] model_read_valid;
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logic scratch_clear;
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logic [19:0] scratch_read_valid;
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logic [19:0][15:0] scratch_read_addr;
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logic [19:0][31:0] scratch_read_data;
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logic [ 5:0] scratch_write_valid;
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logic [ 5:0][15:0] scratch_write_addr;
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logic [ 5:0][31:0] scratch_write_data;
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logic [ 5:0][ 3:0] scratch_write_strb;
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logic scratch_access_err;
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logic [ 7:0] mfcc_bytes [ 0:489];
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logic [ 7:0] expected_layers [0:72087];
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logic use_apum = 1'b0;
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logic check_layers = 1'b0;
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logic [31:0] sequencer_timeout = 32'd0;
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function automatic logic [7:0] synthetic_model_byte(input logic [14:0] address_i);
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begin
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synthetic_model_byte = 8'd0;
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if ((address_i >= 15'h7630) && (address_i < 15'h7660) && (address_i[1:0] == 2'd3)) begin
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synthetic_model_byte = 8'h40;
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end
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case (address_i)
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15'h7614: synthetic_model_byte = 8'he8;
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15'h7615: synthetic_model_byte = 8'h03;
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default: begin
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end
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endcase
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end
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endfunction
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function automatic logic [7:0] scratch_byte(input integer offset_i);
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scratch_byte = u_kws_sram_client.mem[8192+(offset_i/4)][8*(offset_i%4)+:8];
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endfunction
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task automatic check_layer(input integer layer_i);
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integer base;
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integer length;
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logic [7:0] actual;
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begin
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if (layer_i < 9) begin
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base = layer_i * 8000;
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length = 8000;
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end else if (layer_i == 9) begin
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base = 72000;
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length = 64;
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end else begin
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base = 72064;
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length = 12;
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end
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for (int element = 0; element < length; element++) begin
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if (layer_i == 10) begin
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actual = scratch_byte(`RETROSOC_APU_KWS__SCRATCH_LOGITS_BASE + element);
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end else if ((layer_i & 1) != 0) begin
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actual = scratch_byte(`RETROSOC_APU_KWS__SCRATCH_B_BASE + element);
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end else begin
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actual = scratch_byte(`RETROSOC_APU_KWS__SCRATCH_A_BASE + element);
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end
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if (actual != expected_layers[base+element]) begin
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$fatal(1, "KWS layer %0d element %0d mismatch actual=%02x expected=%02x", layer_i,
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element, actual, expected_layers[base+element]);
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end
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end
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end
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endtask
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axi4_stream_if #(
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.DATA_WIDTH(32)
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) stream_i (
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clk_i,
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rst_n_i
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);
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always #5 clk_i = ~clk_i;
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assign stream_i.tvalid = enable_i;
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assign stream_i.tdata = 32'd0;
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assign stream_i.tkeep = 4'hf;
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assign stream_i.tstrb = 4'hf;
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assign stream_i.tlast = 1'b0;
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assign stream_i.tid = '0;
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assign stream_i.tdest = '0;
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assign stream_i.tuser = '0;
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assign stream_i.tready = rx_ready_o;
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for (genvar lane = 0; lane < 16; lane++) begin : gen_model_data
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assign model_data_i[lane] = use_apum ? model_store_data[lane] : synthetic_model_byte(
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model_addr_o[lane]
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);
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end
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apu_kws_sram_client u_kws_sram_client (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.req_i (1'b0),
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.write_i (1'b0),
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.addr_i (17'd0),
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.data_i (32'd0),
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.strb_i (4'd0),
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.ready_o (),
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.data_o (),
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.valid_o (),
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.access_err_o (),
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.access_req_i (storage_req),
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.access_ready_o (storage_ready),
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.access_done_o (storage_done),
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.access_progress_o (storage_progress),
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.access_write_i (storage_write),
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.model_read_valid_i (model_read_valid),
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.model_addr_i (model_addr_o),
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.model_data_o (model_store_data),
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.scratch_clear_i (scratch_clear),
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.scratch_read_valid_i (scratch_read_valid),
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.scratch_read_addr_i (scratch_read_addr),
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.scratch_read_data_o (scratch_read_data),
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.scratch_write_valid_i(scratch_write_valid),
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.scratch_write_addr_i (scratch_write_addr),
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.scratch_write_data_i (scratch_write_data),
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.scratch_write_strb_i (scratch_write_strb),
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.scratch_access_err_o (scratch_access_err)
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);
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apu_kws_engine dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.soft_reset_i (1'b0),
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.resource_reset_i (1'b0),
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.counter_clear_i (counter_clear_i),
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.xrun_clear_i (xrun_clear_i),
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.abort_i (1'b0),
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.quiesce_i (1'b0),
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.disable_i (disable_i),
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.flush_busy_i (flush_busy_i),
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.enable_i (enable_i),
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.memory_window_i (memory_window),
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.clear_history_i (1'b0),
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.model_valid_i (1'b1),
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.model_lock_i (1'b1),
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.sequencer_timeout_i (sequencer_timeout),
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.kws_config_i (16'h0380),
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.memory_start_i (memory_start),
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.memory_start_ready_o (memory_start_ready_o),
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.memory_address_i (32'h0001_0000),
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.memory_dma_request_valid_o (memory_dma_request_valid_o),
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.memory_dma_request_ready_i (memory_dma_request_ready),
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.memory_dma_request_address_o(memory_dma_request_address_o),
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.memory_dma_request_bytes_o (memory_dma_request_bytes_o),
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.memory_dma_data_i (memory_dma_data),
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.memory_dma_keep_i (memory_dma_keep),
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.memory_dma_last_i (memory_dma_last),
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.memory_dma_valid_i (memory_dma_valid),
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.memory_dma_ready_o (memory_dma_ready_o),
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.memory_dma_done_i (memory_dma_done),
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.memory_dma_error_i (memory_dma_error),
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.memory_dma_error_code_i (memory_dma_error_code),
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.memory_dma_error_stage_i (memory_dma_error_stage),
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.memory_dma_error_resp_i (memory_dma_error_resp),
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.memory_dma_error_address_i (memory_dma_error_address),
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.memory_done_o (memory_done_o),
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.memory_error_o (memory_error_o),
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.memory_error_code_o (memory_error_code_o),
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.memory_error_stage_o (memory_error_stage_o),
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.memory_error_resp_o (memory_error_resp_o),
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.memory_error_address_o (memory_error_address_o),
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.memory_error_detail_o (memory_error_detail_o),
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.memory_input_used_o (memory_input_used_o),
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.input_config_i (32'h01043e80),
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.storage_req_o (storage_req),
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.storage_ready_i (storage_ready),
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.storage_done_i (storage_done),
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.storage_progress_i (storage_progress),
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.storage_write_o (storage_write),
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.model_read_valid_o (model_read_valid),
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.model_addr_o (model_addr_o),
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.model_data_i (model_data_i),
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.scratch_clear_o (scratch_clear),
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.scratch_read_valid_o (scratch_read_valid),
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.scratch_read_addr_o (scratch_read_addr),
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.scratch_read_data_i (scratch_read_data),
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.scratch_write_valid_o (scratch_write_valid),
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.scratch_write_addr_o (scratch_write_addr),
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.scratch_write_data_o (scratch_write_data),
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.scratch_write_strb_o (scratch_write_strb),
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.scratch_access_err_i (scratch_access_err),
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.stream_i (stream_i),
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.rx_ready_o (rx_ready_o),
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.status_o (status_o),
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.result_o (result_o),
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.timestamp_lo_o (timestamp_lo_o),
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.timestamp_hi_o (timestamp_hi_o),
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.frame_count_o (frame_count_o),
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.inference_count_o (inference_count_o),
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.hit_count_o (hit_count_o),
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.overrun_count_o (overrun_count_o),
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.model_status_o (model_status_o),
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.model_actual_crc_o (model_actual_crc_o),
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.irq_set_o (irq_set_o),
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.fault_valid_o (fault_valid_o),
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.fault_code_o (fault_code_o),
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.fault_stage_o (fault_stage_o),
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.fault_resp_o (fault_resp_o),
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.fault_index_o (fault_index_o),
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.fault_addr_o (fault_addr_o),
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.fault_detail_o (fault_detail_o),
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.model_valid_o (model_valid_o),
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.model_lock_o (model_lock_o),
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.busy_o (busy_o),
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.idle_o (idle_o)
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);
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initial begin
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integer accepted_samples;
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integer elapsed_cycles;
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string apum_hex;
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string mfcc_hex;
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string layers_hex;
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integer observed_operator;
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repeat (2) @(negedge clk_i);
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rst_n_i = 1'b1;
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@(negedge clk_i);
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if (!model_valid_o || !model_lock_o) $fatal(1, "KWS model admission was not observed");
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dut.s_frame_count_q = 32'd11;
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dut.s_inference_count_q = 32'd12;
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dut.s_hit_count_q = 32'd13;
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dut.s_overrun_count_q = 32'd14;
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dut.s_epoch_samples_q = 32'd1234;
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dut.s_result_q = 32'h0001_5507;
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dut.s_result_valid_q = 1'b1;
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counter_clear_i = 1'b1;
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@(negedge clk_i);
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counter_clear_i = 1'b0;
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if ((frame_count_o != 32'd0) || (inference_count_o != 32'd0) ||
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(hit_count_o != 32'd0) || (overrun_count_o != 32'd0)) begin
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$fatal(1, "KWS counter clear did not clear all four counters");
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end
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if ((dut.s_epoch_samples_q != 32'd1234) || (result_o != 32'h0001_5507) ||
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!status_o[7] || !model_valid_o || !model_lock_o || scratch_clear) begin
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$fatal(1, "KWS counter clear disturbed model, history, result, or scratch state");
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end
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dut.s_overrun_sticky_q = 1'b1;
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xrun_clear_i = 1'b1;
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@(negedge clk_i);
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xrun_clear_i = 1'b0;
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if (status_o[4]) $fatal(1, "KWS stream-xrun W1C did not clear sticky overrun");
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enable_i = 1'b1;
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flush_busy_i = 1'b1;
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xrun_clear_i = 1'b1;
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counter_clear_i = 1'b1;
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@(negedge clk_i);
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enable_i = 1'b0;
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flush_busy_i = 1'b0;
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xrun_clear_i = 1'b0;
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counter_clear_i = 1'b0;
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if (!status_o[4] || !irq_set_o[`APB4_APU__IRQ_STREAM_XRUN] || (overrun_count_o != 32'd0)) begin
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$fatal(1, "KWS hardware overrun did not win stream-xrun clear");
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end
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xrun_clear_i = 1'b1;
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@(negedge clk_i);
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xrun_clear_i = 1'b0;
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if (status_o[4]) $fatal(1, "KWS sticky overrun did not clear after hardware event");
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enable_i = 1'b1;
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@(negedge clk_i);
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if (!status_o[0] || !rx_ready_o) $fatal(1, "KWS listener did not enter continuous capture");
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for (int front_state = 1; front_state <= 8; front_state++) begin
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dut.s_front_state_q = front_state;
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disable_i = 1'b1;
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#1;
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if (!busy_o || !status_o[1] || rx_ready_o) begin
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$fatal(1, "KWS disable did not drain frontend state %0d", front_state);
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end
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dut.s_front_state_q = 4'd0;
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disable_i = 1'b0;
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end
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dut.s_infer_state_q = 4'd2;
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disable_i = 1'b1;
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#1;
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if (!busy_o || !status_o[1] || rx_ready_o) begin
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$fatal(1, "KWS disable did not drain inference");
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end
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dut.s_infer_state_q = 4'd0;
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disable_i = 1'b0;
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dut.s_frame_pending_q = 1'b1;
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disable_i = 1'b1;
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#1;
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if (!busy_o || !status_o[1]) begin
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$fatal(1, "KWS disable ignored pending frontend work");
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end
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dut.s_frame_pending_q = 1'b0;
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disable_i = 1'b0;
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dut.s_mem_dma_active_q = 1'b1;
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dut.s_mem_job_q = 1'b1;
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disable_i = 1'b1;
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#1;
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if (!busy_o || rx_ready_o) $fatal(1, "KWS disable did not drain memory DMA");
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dut.s_mem_dma_active_q = 1'b0;
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dut.s_mem_job_q = 1'b0;
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#1;
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if (!idle_o) begin
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$fatal(
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1,
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"KWS disable did not become idle after drain front=%0d infer=%0d req=%0b dma=%0b job=%0b listen=%0b",
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dut.s_front_state_q, dut.s_infer_state_q, dut.s_mem_req_q, dut.s_mem_dma_active_q,
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dut.s_mem_job_q, dut.s_listening);
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end
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memory_window = 1'b1;
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#1;
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if (!memory_start_ready_o) begin
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$fatal(1, "KWS disable blocked an operation accepted before the drain boundary");
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end
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memory_start = 1'b1;
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@(negedge clk_i);
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memory_start = 1'b0;
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if (!memory_dma_request_valid_o || !busy_o) begin
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$fatal(1, "accepted KWS memory-window job was dropped during disable");
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end
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disable_i = 1'b0;
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memory_window = 1'b0;
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enable_i = 1'b0;
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rst_n_i = 1'b0;
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repeat (2) @(negedge clk_i);
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rst_n_i = 1'b1;
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@(negedge clk_i);
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if ($value$plusargs("APUM_HEX=%s", apum_hex) && $value$plusargs("MFCC_HEX=%s", mfcc_hex)) begin
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$readmemh(apum_hex, u_kws_sram_client.mem, 0, 8191);
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$readmemh(mfcc_hex, mfcc_bytes);
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if ($value$plusargs("LAYERS_HEX=%s", layers_hex)) begin
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$readmemh(layers_hex, expected_layers);
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check_layers = 1'b1;
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end
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use_apum = 1'b1;
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for (int feature = 0; feature < 490; feature++) begin
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u_kws_sram_client.mem[
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8192+((`RETROSOC_APU_KWS__SCRATCH_MFCC_BASE+feature)/4)
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][8*((`RETROSOC_APU_KWS__SCRATCH_MFCC_BASE+feature)%4)+:8] = mfcc_bytes[feature];
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end
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dut.s_operator_q = 4'd0;
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dut.s_output_q = 14'd0;
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dut.s_infer_state_q = 4'd1;
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elapsed_cycles = 0;
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observed_operator = 0;
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while ((inference_count_o == 0) && (elapsed_cycles < 600000)) begin
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@(negedge clk_i);
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if (check_layers && (dut.s_operator_q != observed_operator)) begin
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check_layer(observed_operator);
|
|
observed_operator = dut.s_operator_q;
|
|
end
|
|
elapsed_cycles++;
|
|
end
|
|
if ((inference_count_o != 1) || (result_o[7:0] != 8'd7)) begin
|
|
$display(
|
|
"golden inference=%0d result=%08x fault=%0b/%0d stage=%0d detail=%08x op=%0d output=%0d",
|
|
inference_count_o, result_o, fault_valid_o, fault_code_o, fault_stage_o,
|
|
fault_detail_o, dut.s_operator_q, dut.s_output_q);
|
|
for (int class_index = 0; class_index < 12; class_index++) begin
|
|
$display("class=%0d logits=%0d softmax=%0d", class_index, scratch_byte(
|
|
`RETROSOC_APU_KWS__SCRATCH_LOGITS_BASE + class_index), scratch_byte(
|
|
`RETROSOC_APU_KWS__SCRATCH_SOFTMAX_BASE + class_index));
|
|
end
|
|
$fatal(1, "frozen APUM inference did not classify the official Stop feature");
|
|
end
|
|
for (int class_index = 0; class_index < 12; class_index++) begin
|
|
if (check_layers && (scratch_byte(
|
|
`RETROSOC_APU_KWS__SCRATCH_SOFTMAX_BASE + class_index
|
|
) != expected_layers[72076+class_index])) begin
|
|
$fatal(1, "frozen APUM inference Softmax byte mismatch");
|
|
end
|
|
end
|
|
rst_n_i = 1'b0;
|
|
repeat (2) @(negedge clk_i);
|
|
use_apum = 1'b0;
|
|
rst_n_i = 1'b1;
|
|
@(negedge clk_i);
|
|
end
|
|
|
|
memory_window = 1'b1;
|
|
enable_i = 1'b1;
|
|
memory_start = 1'b1;
|
|
@(negedge clk_i);
|
|
memory_start = 1'b0;
|
|
wait (memory_dma_request_valid_o);
|
|
if ((memory_dma_request_address_o != 32'h0001_0000) ||
|
|
(memory_dma_request_bytes_o != 32'd32000)) begin
|
|
$fatal(1, "KWS memory DMA request mismatch");
|
|
end
|
|
memory_dma_request_ready = 1'b1;
|
|
@(negedge clk_i);
|
|
memory_dma_request_ready = 1'b0;
|
|
for (int word_index = 0; word_index < 8000; word_index++) begin
|
|
memory_dma_data = 32'd0;
|
|
memory_dma_keep = 4'hf;
|
|
memory_dma_last = word_index == 7999;
|
|
memory_dma_valid = 1'b1;
|
|
do @(negedge clk_i); while (!memory_dma_ready_o);
|
|
end
|
|
memory_dma_valid = 1'b0;
|
|
memory_dma_last = 1'b0;
|
|
memory_dma_done = 1'b1;
|
|
@(negedge clk_i);
|
|
memory_dma_done = 1'b0;
|
|
elapsed_cycles = 0;
|
|
while (!memory_done_o && (elapsed_cycles < 3000000)) begin
|
|
@(negedge clk_i);
|
|
elapsed_cycles++;
|
|
end
|
|
if (!memory_done_o || memory_error_o || (frame_count_o != 32'd49) ||
|
|
(inference_count_o != 32'd1) || (result_o[7:0] != 8'd5) ||
|
|
(memory_input_used_o != 32'd32000)) begin
|
|
$fatal(1, "bounded KWS memory job did not complete with a fresh result");
|
|
end
|
|
|
|
rst_n_i = 1'b0;
|
|
enable_i = 1'b0;
|
|
memory_window = 1'b0;
|
|
repeat (2) @(negedge clk_i);
|
|
rst_n_i = 1'b1;
|
|
enable_i = 1'b1;
|
|
memory_window = 1'b1;
|
|
memory_start = 1'b1;
|
|
@(negedge clk_i);
|
|
memory_start = 1'b0;
|
|
wait (memory_dma_request_valid_o);
|
|
memory_dma_request_ready = 1'b1;
|
|
@(negedge clk_i);
|
|
memory_dma_request_ready = 1'b0;
|
|
memory_dma_error = 1'b1;
|
|
memory_dma_error_code = `APB4_APU__ERROR_CODE_AXI_READ;
|
|
memory_dma_error_stage = `APB4_APU__ERROR_STAGE_DMA_READ;
|
|
memory_dma_error_resp = 2'd2;
|
|
memory_dma_error_address = 32'h0001_2340;
|
|
memory_dma_done = 1'b1;
|
|
@(negedge clk_i);
|
|
memory_dma_done = 1'b0;
|
|
memory_dma_error = 1'b0;
|
|
wait (memory_done_o);
|
|
if (!memory_error_o || (memory_error_code_o != `APB4_APU__ERROR_CODE_AXI_READ) ||
|
|
(memory_error_stage_o != `APB4_APU__ERROR_STAGE_DMA_READ) ||
|
|
(memory_error_resp_o != 2'd2) || (memory_error_address_o != 32'h0001_2340) ||
|
|
(memory_error_detail_o != 32'd0)) begin
|
|
$fatal(1, "KWS memory DMA failure did not preserve its exact tuple");
|
|
end
|
|
|
|
rst_n_i = 1'b0;
|
|
enable_i = 1'b0;
|
|
memory_window = 1'b0;
|
|
repeat (2) @(negedge clk_i);
|
|
rst_n_i = 1'b1;
|
|
@(negedge clk_i);
|
|
enable_i = 1'b1;
|
|
accepted_samples = 0;
|
|
elapsed_cycles = 0;
|
|
while ((accepted_samples < 16000) && (elapsed_cycles < 4000000)) begin
|
|
@(posedge clk_i);
|
|
if (stream_i.tvalid && stream_i.tready) accepted_samples++;
|
|
elapsed_cycles++;
|
|
end
|
|
if (accepted_samples != 16000) begin
|
|
$fatal(
|
|
1,
|
|
"KWS input timeout accepted=%0d front=%0d infer=%0d wait=%0b req=%0b ready=%0b done=%0b",
|
|
accepted_samples, dut.s_front_state_q, dut.s_infer_state_q, dut.s_storage_wait_q,
|
|
storage_req, storage_ready, storage_done);
|
|
end
|
|
@(negedge clk_i);
|
|
enable_i = 1'b0;
|
|
elapsed_cycles = 0;
|
|
while ((inference_count_o == 0) && (elapsed_cycles < 4000000)) begin
|
|
@(negedge clk_i);
|
|
elapsed_cycles++;
|
|
end
|
|
if (frame_count_o != 49 || inference_count_o != 1 || !status_o[7]) begin
|
|
$display(
|
|
"accepted=%0d elapsed=%0d frames=%0d inferences=%0d status=%08x fault=%0b/%0d stage=%0d detail=%08x front=%0d infer=%0d op=%0d output=%0d term=%0d",
|
|
accepted_samples, elapsed_cycles, frame_count_o, inference_count_o, status_o,
|
|
fault_valid_o, fault_code_o, fault_stage_o, fault_detail_o, dut.s_front_state_q,
|
|
dut.s_infer_state_q, dut.s_operator_q, dut.s_output_q, dut.s_term_q);
|
|
$fatal(1, "KWS continuous window did not complete");
|
|
end
|
|
if (result_o[7:0] != 8'd5) $fatal(1, "KWS result did not depend on model SRAM data");
|
|
|
|
rst_n_i = 1'b0;
|
|
enable_i = 1'b0;
|
|
repeat (2) @(negedge clk_i);
|
|
sequencer_timeout = 32'd3;
|
|
rst_n_i = 1'b1;
|
|
@(negedge clk_i);
|
|
enable_i = 1'b1;
|
|
elapsed_cycles = 0;
|
|
while (!fault_valid_o && (elapsed_cycles < 2000)) begin
|
|
@(negedge clk_i);
|
|
elapsed_cycles++;
|
|
end
|
|
if (!fault_valid_o || (fault_code_o != 6'd14) || (fault_stage_o != 4'd9)) begin
|
|
$fatal(1, "KWS frontend no-progress watchdog did not fail closed");
|
|
end
|
|
$display("APU-P7 KWS engine directed test passed");
|
|
$finish;
|
|
end
|
|
endmodule
|