mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
7592808464
- Updated the JPEG table register bank module to use combinational logic for data handling and simplified the write logic for quantization, DC, and AC entries. - Introduced a new function in the run_flow script to handle process termination more gracefully, including signal handling for interrupts. - Enhanced the flow script to log peak RSS memory usage during execution. - Modified multiple testbench files to include new storage access signals and improved the test logic for better validation of KWS and SRAM interactions. - Updated tests to validate the new peak RSS memory logging in the flow script. - Adjusted Yosys synthesis recipes to include timeout settings and ensure proper reporting of pre-memory synthesis outputs.
246 lines
8.7 KiB
Systemverilog
246 lines
8.7 KiB
Systemverilog
`timescale 1ns / 1ps
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module apu_kws_sram_client_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic req_i = 1'b0;
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logic write_i = 1'b1;
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logic [16:0] addr_i = 17'd0;
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logic [31:0] data_i = 32'd0;
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logic [ 3:0] strb_i = 4'd0;
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logic ready_o, valid_o, access_err_o;
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logic [31:0] data_o;
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logic access_req_i = 1'b0;
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logic access_ready_o, access_done_o, access_progress_o;
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logic access_write_i = 1'b0;
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logic [15:0] model_read_valid_i = 16'd0;
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logic [15:0][14:0] model_addr_i = '0;
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logic [15:0][ 7:0] model_data_o;
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logic scratch_clear_i = 1'b0;
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logic [19:0] scratch_read_valid_i = 20'd0;
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logic [19:0][15:0] scratch_read_addr_i = '0;
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logic [19:0][31:0] scratch_read_data_o;
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logic [ 5:0] scratch_write_valid_i = 6'd0;
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logic [ 5:0][15:0] scratch_write_addr_i = '0;
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logic [ 5:0][31:0] scratch_write_data_i = '0;
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logic [ 5:0][ 3:0] scratch_write_strb_i = '0;
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logic scratch_access_err_o;
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logic codec_req_i = 1'b0;
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logic [16:0] codec_addr_i = 17'd0;
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logic codec_ready_o, codec_valid_o, codec_access_err_o;
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logic [31:0] codec_data_o;
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always #5 clk_i = ~clk_i;
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apu_kws_sram_client u_kws_sram_client (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.req_i (req_i),
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.write_i (write_i),
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.addr_i (addr_i),
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.data_i (data_i),
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.strb_i (strb_i),
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.ready_o (ready_o),
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.data_o (data_o),
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.valid_o (valid_o),
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.access_err_o (access_err_o),
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.access_req_i (access_req_i),
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.access_ready_o (access_ready_o),
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.access_done_o (access_done_o),
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.access_progress_o (access_progress_o),
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.access_write_i (access_write_i),
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.model_read_valid_i (model_read_valid_i),
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.model_addr_i (model_addr_i),
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.model_data_o (model_data_o),
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.scratch_clear_i (scratch_clear_i),
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.scratch_read_valid_i (scratch_read_valid_i),
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.scratch_read_addr_i (scratch_read_addr_i),
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.scratch_read_data_o (scratch_read_data_o),
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.scratch_write_valid_i(scratch_write_valid_i),
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.scratch_write_addr_i (scratch_write_addr_i),
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.scratch_write_data_i (scratch_write_data_i),
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.scratch_write_strb_i (scratch_write_strb_i),
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.scratch_access_err_o (scratch_access_err_o)
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);
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apu_local_sram u_local_sram (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.image_valid_i (1'b1),
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.table_bytes_i (16'd0),
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.epoch_clear_i (1'b0),
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.loader_active_i (1'b0),
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.loader_req_i (1'b0),
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.loader_addr_i (17'd0),
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.loader_data_i (32'd0),
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.loader_strb_i (4'd0),
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.loader_ready_o (),
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.codec_req_i (codec_req_i),
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.codec_write_i (1'b0),
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.codec_addr_i (codec_addr_i),
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.codec_data_i (32'd0),
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.codec_strb_i (4'd0),
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.codec_ready_o (codec_ready_o),
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.codec_data_o (codec_data_o),
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.codec_valid_o (codec_valid_o),
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.codec_access_err_o(codec_access_err_o)
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);
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task automatic write_model(input logic [16:0] address_i, input logic [31:0] value_i);
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begin
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@(negedge clk_i);
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req_i = 1'b1;
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addr_i = address_i;
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data_i = value_i;
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strb_i = 4'hf;
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if (!ready_o) $fatal(1, "model client did not accept a bounded write");
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@(negedge clk_i);
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req_i = 1'b0;
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strb_i = 4'd0;
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end
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endtask
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task automatic run_access(input logic write_access_i);
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begin
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@(negedge clk_i);
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access_write_i = write_access_i;
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access_req_i = 1'b1;
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if (!access_ready_o) $fatal(1, "KWS SRAM transaction was not accepted");
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@(negedge clk_i);
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access_req_i = 1'b0;
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wait (access_done_o);
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@(negedge clk_i);
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access_write_i = 1'b0;
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end
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endtask
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task automatic write_scratch(input logic [15:0] address_i, input logic [31:0] value_i,
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input logic [3:0] strobe_i);
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begin
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@(negedge clk_i);
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scratch_write_valid_i[0] = 1'b1;
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scratch_write_addr_i[0] = address_i;
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scratch_write_data_i[0] = value_i;
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scratch_write_strb_i[0] = strobe_i;
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run_access(1'b1);
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scratch_write_valid_i[0] = 1'b0;
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scratch_write_strb_i[0] = 4'd0;
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scratch_read_addr_i[0] = address_i;
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scratch_read_valid_i[0] = 1'b1;
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run_access(1'b0);
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scratch_read_valid_i[0] = 1'b0;
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if (scratch_read_data_o[0] != value_i) begin
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$fatal(1, "scratch layout write mismatch at %04x", address_i);
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end
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end
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endtask
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task automatic reject_codec_address(input logic [16:0] address_i);
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begin
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@(negedge clk_i);
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codec_req_i = 1'b1;
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codec_addr_i = address_i;
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#1;
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if (!codec_ready_o || !codec_access_err_o) begin
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$fatal(1, "codec accessed reserved KWS bank at %05x", address_i);
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end
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@(negedge clk_i);
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codec_req_i = 1'b0;
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end
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endtask
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initial begin
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repeat (3) @(negedge clk_i);
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rst_n_i = 1'b1;
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write_model(`APB4_APU__LOCAL_KWS_BASE, 32'h4433_2211);
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model_addr_i[0] = 15'd0;
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model_addr_i[1] = 15'd1;
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model_addr_i[2] = 15'd2;
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model_addr_i[3] = 15'd3;
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model_read_valid_i[3:0] = 4'hf;
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run_access(1'b0);
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model_read_valid_i = 16'd0;
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if ({model_data_o[3], model_data_o[2], model_data_o[1], model_data_o[0]} != 32'h4433_2211) begin
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$fatal(1, "banks10..17 model readback mismatch");
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end
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write_model(17'h1_0000, 32'h8877_6655);
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write_model(`APB4_APU__LOCAL_KWS_BASE + `RETROSOC_APU_KWS__MODEL_BYTES - 4, 32'hccbb_aa99);
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model_addr_i[0] = 15'h6000;
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model_addr_i[1] = 15'h6001;
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model_addr_i[2] = 15'h6002;
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model_addr_i[3] = 15'h6003;
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model_addr_i[4] = 15'h7ffc;
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model_addr_i[5] = 15'h7ffd;
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model_addr_i[6] = 15'h7ffe;
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model_addr_i[7] = 15'h7fff;
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model_read_valid_i[7:0] = 8'hff;
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run_access(1'b0);
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model_read_valid_i = 16'd0;
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if ({model_data_o[3], model_data_o[2], model_data_o[1], model_data_o[0]} != 32'h8877_6655) begin
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$fatal(1, "APUM model address crossing 0x10000 did not map to bank16");
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end
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if ({model_data_o[7], model_data_o[6], model_data_o[5], model_data_o[4]} != 32'hccbb_aa99) begin
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$fatal(1, "APUM final word did not map to bank17");
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end
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write_scratch(`RETROSOC_APU_KWS__SCRATCH_A_BASE, 32'h0102_0304, 4'hf);
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write_scratch(`RETROSOC_APU_KWS__SCRATCH_B_BASE, 32'h1112_1314, 4'hf);
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write_scratch(`RETROSOC_APU_KWS__SCRATCH_MFCC_BASE, 32'h2122_2324, 4'hf);
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write_scratch(`RETROSOC_APU_KWS__SCRATCH_MEL_BASE, 32'h3132_3334, 4'hf);
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write_scratch(`RETROSOC_APU_KWS__SCRATCH_FFT_REAL_BASE, 32'h4142_4344, 4'hf);
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write_scratch(`RETROSOC_APU_KWS__SCRATCH_INGRESS_BASE, 32'h5152_5354, 4'hf);
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write_scratch(`RETROSOC_APU_KWS__SCRATCH_PEAK_BASE, 32'h6162_6364, 4'hf);
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write_scratch(16'h7ffc, 32'h7172_7374, 4'hf);
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model_addr_i[0] = 15'd0;
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model_read_valid_i[0] = 1'b1;
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run_access(1'b0);
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model_read_valid_i = 16'd0;
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if (model_data_o[0] != 8'h11) $fatal(1, "scratch write corrupted APUM storage");
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@(negedge clk_i);
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req_i = 1'b1;
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addr_i = `RETROSOC_APU_KWS__SCRATCH_LOCAL_BASE;
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#1;
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if (!access_err_o) $fatal(1, "model loader escaped banks10..17");
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@(negedge clk_i);
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req_i = 1'b0;
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@(negedge clk_i);
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scratch_write_addr_i[0] = 16'h8000;
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scratch_write_valid_i[0] = 1'b1;
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#1;
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if (!scratch_access_err_o) $fatal(1, "scratch range overflow was accepted");
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@(negedge clk_i);
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scratch_write_valid_i[0] = 1'b0;
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write_scratch(`RETROSOC_APU_KWS__SCRATCH_FIR_BASE, 32'h0000_1234, 4'hf);
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@(negedge clk_i);
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scratch_clear_i = 1'b1;
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@(negedge clk_i);
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scratch_clear_i = 1'b0;
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scratch_read_addr_i[0] = `RETROSOC_APU_KWS__SCRATCH_FIR_BASE;
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scratch_read_valid_i[0] = 1'b1;
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run_access(1'b0);
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scratch_read_valid_i[0] = 1'b0;
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if (scratch_read_data_o[0] != 32'd0) $fatal(1, "FIR lifecycle clear exposed stale data");
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scratch_read_addr_i[0] = `RETROSOC_APU_KWS__SCRATCH_A_BASE;
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scratch_read_valid_i[0] = 1'b1;
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run_access(1'b0);
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scratch_read_valid_i[0] = 1'b0;
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if (scratch_read_data_o[0] != 32'h0102_0304) begin
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$fatal(1, "history clear corrupted non-history scratch");
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end
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reject_codec_address(`APB4_APU__LOCAL_KWS_BASE);
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reject_codec_address(`RETROSOC_APU_KWS__SCRATCH_LOCAL_BASE);
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$display("PASS: APU P7 banks10..25 model/scratch SRAM isolation");
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$finish;
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end
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logic s_unused;
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assign s_unused = valid_o ^ ^data_o ^ codec_valid_o ^ ^codec_data_o ^ access_progress_o;
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endmodule
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