mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
795559f785
- Introduced sysctrl_define.svh to define register offsets and constants for SysCtrl. - Created sysctrl_if.sv interface for communication with SysCtrl. - Implemented sysctrl_reg.sv module to handle register read/write operations and state management. - Developed sysctrl_tb.sv testbench to validate SysCtrl functionality, including lifecycle, fault handling, performance monitoring, and RTC wake status. - Added Python regression test (test_sysctrl.py) to automate SysCtrl verification using Icarus Verilog.
109 lines
7.7 KiB
C
109 lines
7.7 KiB
C
#ifndef _RETROSOC_DEF_H_
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#define _RETROSOC_DEF_H_
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#include <stdint.h>
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#include <stdbool.h>
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#include <retrosoc/generated/memory_map.h>
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#include <retrosoc/generated/user_extensions.h>
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#define HW_CORE "Management Hazard3"
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#define CPU_FREQ 72 // unit: MHz
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#define UART_BPS 921600 // unit: bps
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#define SPFS_MEM_START RS_SOC_FLASH_BASE
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#define SPFS_MEM_OFFST RS_SOC_FLASH_SIZE
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#define SRAM_MEM_START RS_SOC_SRAM_BASE
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#define SRAM_MEM_OFFST RS_SOC_SRAM_SIZE
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#define SDRAM_MEM_START RS_SOC_SDRAM_BASE
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#define SDRAM_MEM_OFFST RS_SOC_SDRAM_SIZE
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#define PSRAM_MEM_START RS_SOC_PSRAM_BASE
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#define PSRAM_MEM_OFFST RS_SOC_PSRAM_SIZE
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#define XPI_MEM_START RS_SOC_XPI_BASE
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#define XPI_MEM_OFFST RS_SOC_XPI_SIZE
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#define TF_CARD_START RS_SOC_SPISD_BASE
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#define TF_CARD_OFFST RS_SOC_SPISD_SIZE
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#define RS_SOC_REG32(base, offset) (*(volatile uint32_t *)(uintptr_t)((base) + (offset)))
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// spisd
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#define reg_spisd_mode RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x00))
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#define reg_spisd_clkdiv RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x04))
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#define reg_spisd_addr RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x08))
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#define reg_spisd_txdata RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x0C))
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#define reg_spisd_rxdata RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x10))
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#define reg_spisd_status RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x14))
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#define reg_spisd_sync RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x18))
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// i2s
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#define reg_i2s_mode RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x00))
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#define reg_i2s_format RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x04))
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#define reg_i2s_upbound RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x08))
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#define reg_i2s_lowbound RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x0C))
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#define reg_i2s_recven RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x10))
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#define reg_i2s_txdata RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x14))
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#define reg_i2s_rxdata RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x18))
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#define reg_i2s_status RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x1C))
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#define reg_i2s_stream_ctrl RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x20))
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// xpi
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#define reg_xpi_cfgidx RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x00))
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#define reg_xpi_accmd RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x04))
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#define reg_xpi_mmstad RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x08))
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#define reg_xpi_mmoffst RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x0C))
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#define reg_xpi_mode RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x10))
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#define reg_xpi_nss RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x14))
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#define reg_xpi_clkdiv RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x18))
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#define reg_xpi_rdwr RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x1C))
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#define reg_xpi_revdat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x20))
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#define reg_xpi_txupb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x24))
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#define reg_xpi_txlowb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x28))
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#define reg_xpi_rxupb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x2C))
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#define reg_xpi_rxlowb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x30))
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#define reg_xpi_flush RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x34))
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#define reg_xpi_cmdtyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x38))
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#define reg_xpi_cmdlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x3C))
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#define reg_xpi_cmddat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x40))
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#define reg_xpi_adrtyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x44))
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#define reg_xpi_adrlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x48))
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#define reg_xpi_adrdat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x4C))
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#define reg_xpi_alttyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x50))
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#define reg_xpi_altlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x54))
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#define reg_xpi_altdat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x58))
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#define reg_xpi_tdulen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x5C))
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#define reg_xpi_rdulen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x60))
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#define reg_xpi_dattyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x64))
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#define reg_xpi_datlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x68))
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#define reg_xpi_datbit RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x6C))
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#define reg_xpi_hlvlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x70))
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#define reg_xpi_txdata RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x74))
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#define reg_xpi_rxdata RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x78))
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#define reg_xpi_start RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x7C))
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#define reg_xpi_status RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x80))
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// dma(32b xfer, hardware trigger by I2S fifo, QSPI fifo)
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#define reg_dma_mode RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x00))
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#define reg_dma_srcaddr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x04))
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#define reg_dma_srcincr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x08))
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#define reg_dma_dstaddr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x0C))
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#define reg_dma_dstincr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x10))
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#define reg_dma_xferlen RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x14))
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#define reg_dma_start RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x18))
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#define reg_dma_stop RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x1C))
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#define reg_dma_reset RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x20))
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#define reg_dma_status RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x24))
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#define reg_dma_fsm RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x28))
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#define reg_dma_error_status RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x2C))
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#define reg_dma_error_addr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x30))
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#define RS_SOC_DMA_ERROR_PENDING UINT32_C(0x00000001)
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#define RS_SOC_DMA_ERROR_RESPONSE_SHIFT 1U
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#define RS_SOC_DMA_ERROR_RESPONSE_MASK UINT32_C(0x0000000E)
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// sdram
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#define reg_sdram_clkdiv RS_SOC_REG32(RS_SOC_RIBP_SDRAM_BASE, UINT32_C(0x00))
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#define reg_sdram_cfg RS_SOC_REG32(RS_SOC_RIBP_SDRAM_BASE, UINT32_C(0x04))
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#define reg_user_ip_reg0 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x00))
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#define reg_user_ip_reg1 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x04))
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#define reg_user_ip_reg2 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x08))
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#define reg_user_ip_reg3 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x0C))
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#define reg_user_ip_reg4 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x10))
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#define reg_user_ip_reg5 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x14))
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#define reg_user_ip_reg6 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x18))
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#endif
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