mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
7a604ec86b
- Removed CORE and IP variables from common.tcl and synth.tcl scripts. - Updated yosys.mk to exclude CORE and IP from environment variables. - Modified bus_fault_tb to enhance NMI interface with management and user NMI signals. - Added user access denial handling in bus_fault_tb. - Updated pll_ctrl_tb and sysctrl_fault_tb to reflect changes in NMI interface. - Adjusted test_gpio_user_mux.py to remove IP_MDD definition. - Enhanced memory map tests to include user extensions and ensure proper generation. - Updated test_script_tools.py to reflect changes in core management and user extensions. - Refined topology tests to ensure user APB target is always added. - Adjusted tech cell configuration tests to use simplified profile paths. - Improved user extensions tests for scalar bindings and slot validation.
92 lines
2.7 KiB
Systemverilog
92 lines
2.7 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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module gpio_user_formal_design (
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input logic clk_i,
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output logic rst_n_i,
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output logic f_past_valid,
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output logic nmi_valid,
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output logic [31:0] nmi_addr,
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output logic [31:0] nmi_wdata,
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output logic [ 3:0] nmi_wstrb,
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output logic nmi_ready,
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output logic [31:0] gpio_di,
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output logic [31:0] gpio_oe,
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output logic [31:0] gpio_do,
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output logic [31:0] user_di,
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output logic [31:0] user_oe,
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output logic [31:0] user_do,
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output logic [31:0] user_sel,
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output logic [31:0] user_lock,
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output logic [31:0] user_handoff,
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output logic [31:0] user_status,
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output logic [31:0] native_oe,
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output logic [31:0] native_do
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);
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nmi_if nmi ();
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gpio_if gpio ();
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user_gpio_if user_gpio ();
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(* anyseq *)logic f_nmi_valid;
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(* anyseq *)logic [31:0] f_nmi_addr;
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(* anyseq *)logic [31:0] f_nmi_wdata;
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(* anyseq *)logic [ 3:0] f_nmi_wstrb;
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(* anyseq *)logic [31:0] f_gpio_di;
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(* anyseq *)logic [31:0] f_alt0_do;
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(* anyseq *)logic [31:0] f_alt0_oe;
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(* anyseq *)logic [31:0] f_alt1_do;
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(* anyseq *)logic [31:0] f_alt1_oe;
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(* anyseq *)logic [31:0] f_user_do;
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(* anyseq *)logic [31:0] f_user_oe;
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assign nmi.valid = f_nmi_valid;
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assign nmi.addr = f_nmi_addr;
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assign nmi.wdata = f_nmi_wdata;
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assign nmi.wstrb = f_nmi_wstrb;
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assign gpio.di_i = f_gpio_di;
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assign gpio.alt0_do_i = f_alt0_do;
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assign gpio.alt0_oe_i = f_alt0_oe;
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assign gpio.alt1_do_i = f_alt1_do;
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assign gpio.alt1_oe_i = f_alt1_oe;
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assign user_gpio.do_o = f_user_do;
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assign user_gpio.oe_o = f_user_oe;
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assign nmi_valid = nmi.valid;
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assign nmi_addr = nmi.addr;
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assign nmi_wdata = nmi.wdata;
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assign nmi_wstrb = nmi.wstrb;
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assign nmi_ready = nmi.ready;
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assign gpio_di = gpio.di_i;
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assign gpio_oe = gpio.oe_o;
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assign gpio_do = gpio.do_o;
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assign user_di = user_gpio.di_i;
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assign user_oe = user_gpio.oe_o;
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assign user_do = user_gpio.do_o;
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assign user_sel = u_dut.s_gpio_user_sel_q;
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assign user_lock = u_dut.s_gpio_user_lock_q;
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assign user_handoff = u_dut.s_gpio_user_handoff_q;
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assign user_status = u_dut.s_gpio_user_status;
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assign native_oe = u_dut.s_gpio_native_oe;
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assign native_do = u_dut.s_gpio_native_out;
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nmi_gpio u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.nmi (nmi),
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.gpio (gpio),
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.user_gpio(user_gpio)
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);
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initial begin
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rst_n_i = 1'b0;
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f_past_valid = 1'b0;
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end
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always_ff @(posedge clk_i) begin
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rst_n_i <= 1'b1;
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f_past_valid <= 1'b1;
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end
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endmodule
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