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https://github.com/retroSoC/retroSoC.git
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maksyuki
7c923687ff
- Introduced new JSON files for warnings generated by Icarus Verilog, Verilator, and Yosys for both GF180 and SKY130 PDKs. - Updated the build requirements to include necessary packages for handling JSON data. - Modified RTL filelists to use generated files for GF180 and SKY130 standard-cell models. - Enhanced the Iverilog makefile to generate filelists dynamically based on the selected PDK. - Implemented a Python script to generate Iverilog filelists, accommodating both GF180 and SKY130 technologies. - Added behavioral definitions for GF180 UDPs and a tri-state buffer for netlist simulations. - Updated Yosys synthesis scripts to handle new PDKs and ensure proper tie cell mapping. - Extended regression scripts to support PDK-specific commands for GF180 and SKY130. - Added tests to verify that PDK-specific regression commands cover firmware, RTL, and netlist simulations.
Reproducible Build Profiles
This directory contains committed Make configuration profiles. Each profile selects SoC, CPU/IP, PDK, ISA, CSR support, application, linker layout, and the supported validation tier.
ci/ contains pull-request profiles, nightly/ adds extended open-source
coverage, and cluster/ contains configurations requiring site tools or PDKs.
Start builds from a committed profile rather than setting an unreviewed mix of
variables on the command line.
For supported profiles and commands, see the root README and agent contract.