mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
82e5c605a8
- Updated core_wrapper and mgmt_core_wrapper to use new SOC reset and IRQ addresses. - Removed obsolete mmap_define.svh file and integrated memory map generation into the build process. - Enhanced ip_nmi_wrapper to handle fault signals and updated NMI interface assignments. - Added bus fault and sysctrl fault testbenches to validate fault handling mechanisms. - Improved memory map generation script and added tests for memory map validation and fault responder behavior.
78 lines
2.1 KiB
Systemverilog
78 lines
2.1 KiB
Systemverilog
`timescale 1ns / 1ps
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module bus_fault_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic fault_valid_o;
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logic [31:0] fault_addr_o;
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logic [ 3:0] fault_wstrb_o;
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logic fault_reserved_o;
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nmi_if core_nmi ();
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nmi_if dma_nmi ();
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nmi_if natv_nmi ();
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nmi_if apb_nmi ();
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always #5 clk_i = ~clk_i;
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assign natv_nmi.ready = 1'b1;
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assign natv_nmi.rdata = 32'hCAFE_BABE;
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assign apb_nmi.ready = 1'b1;
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assign apb_nmi.rdata = 32'h1234_5678;
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bus u_bus (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.core_nmi (core_nmi),
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.dma_nmi (dma_nmi),
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.natv_nmi (natv_nmi),
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.apb_nmi (apb_nmi),
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.fault_valid_o (fault_valid_o),
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.fault_addr_o (fault_addr_o),
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.fault_wstrb_o (fault_wstrb_o),
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.fault_reserved_o(fault_reserved_o)
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);
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task automatic expect_fault(input logic [31:0] address, input logic [3:0] write_strobes,
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input logic reserved);
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begin
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@(negedge clk_i);
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core_nmi.addr = address;
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core_nmi.wdata = 32'hA5A5_5A5A;
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core_nmi.wstrb = write_strobes;
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core_nmi.valid = 1'b1;
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while (!fault_valid_o) @(posedge clk_i);
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if (fault_addr_o !== address || fault_wstrb_o !== write_strobes ||
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fault_reserved_o !== reserved || natv_nmi.valid || apb_nmi.valid) begin
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$fatal(1, "unexpected fault response for address %h", address);
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end
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while (!core_nmi.ready) @(posedge clk_i);
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if (core_nmi.rdata !== 32'd0) begin
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$fatal(1, "fault response data must be zero");
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end
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@(negedge clk_i);
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core_nmi.valid = 1'b0;
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while (fault_valid_o) @(posedge clk_i);
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end
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endtask
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initial begin
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core_nmi.valid = 1'b0;
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core_nmi.addr = '0;
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core_nmi.wdata = '0;
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core_nmi.wstrb = '0;
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dma_nmi.valid = 1'b0;
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dma_nmi.addr = '0;
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dma_nmi.wdata = '0;
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dma_nmi.wstrb = '0;
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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expect_fault(32'h1000_F000, 4'hF, 1'b1);
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expect_fault(32'hA000_0000, 4'h0, 1'b0);
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$display("bus fault responder test passed");
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$finish;
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end
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endmodule
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