mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine. - Updated clock and reset domain tests to include USB2 ULPI crossings. - Enhanced memory map tests to verify USB2 base addresses and performance offsets. - Modified pin map tests to ensure USB2 ULPI pins are correctly generated. - Updated SOC topology tests to account for USB2 peripherals and IRQ mappings. - Added static timing analysis constraints for USB2 clock domains. - Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine. - Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
39 lines
1.3 KiB
Systemverilog
39 lines
1.3 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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module usb2_pkg_tb;
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logic [15:0] s_crc16;
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initial begin
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if (usb2_pkg::usb2_pid_byte(usb2_pkg::Usb2PidOut) != 8'hE1) begin
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$fatal(1, "USB2 OUT PID encoding mismatch");
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end
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if (!usb2_pkg::usb2_pid_valid(8'hD2) || usb2_pkg::usb2_pid_valid(8'h52)) begin
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$fatal(1, "USB2 PID complement validation mismatch");
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end
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if (usb2_pkg::usb2_token_crc5(
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11'd0
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) != 5'h02 || usb2_pkg::usb2_token_crc5(
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11'd1
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) != 5'h1D) begin
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$fatal(1, "USB2 token CRC5 vector mismatch");
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end
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s_crc16 = 16'hFFFF;
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s_crc16 = usb2_pkg::usb2_crc16_byte(s_crc16, "1");
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s_crc16 = usb2_pkg::usb2_crc16_byte(s_crc16, "2");
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s_crc16 = usb2_pkg::usb2_crc16_byte(s_crc16, "3");
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s_crc16 = usb2_pkg::usb2_crc16_byte(s_crc16, "4");
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s_crc16 = usb2_pkg::usb2_crc16_byte(s_crc16, "5");
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s_crc16 = usb2_pkg::usb2_crc16_byte(s_crc16, "6");
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s_crc16 = usb2_pkg::usb2_crc16_byte(s_crc16, "7");
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s_crc16 = usb2_pkg::usb2_crc16_byte(s_crc16, "8");
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s_crc16 = usb2_pkg::usb2_crc16_byte(s_crc16, "9");
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if (usb2_pkg::usb2_crc16_finish(s_crc16) != 16'hB4C8) begin
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$fatal(1, "USB2 CRC16 vector mismatch");
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end
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$display("USB2 PID and CRC vectors passed");
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$finish;
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end
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endmodule
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