mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
87df13fb46
- Introduced a new ECC directory containing scripts and Makefile for the padless ICS55 core hardening flow. - Updated the main Makefile to include the new ECC Makefile and added relevant help commands. - Added dependencies for the ECC CLI in the dependencies.lock.json file. - Created README documentation for the ECC flow detailing usage and requirements. - Implemented various scripts for configuration generation, validation, output checking, and packaging of ECC results. - Added unit tests to validate the ECC configuration and flow behavior.
108 lines
3.6 KiB
Python
108 lines
3.6 KiB
Python
#!/usr/bin/env python3
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"""Generate a padless ICS55 ECC project configuration from canonical inputs."""
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from __future__ import annotations
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import argparse
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import os
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from pathlib import Path
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EXPECTED_CLOCKS = (
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"clk_external",
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"clk_system",
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"clk_audio",
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"clk_jtag",
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"clk_dvp",
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"clk_usb2_ulpi",
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)
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def relative(path: Path, base: Path) -> str:
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return os.path.relpath(path.resolve(), base.resolve())
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def render(args: argparse.Namespace) -> str:
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project_dir = args.output.resolve().parent
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pdk_root = args.pdk_root.resolve()
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sdc = args.sdc.resolve()
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liberty = args.h7cr_liberty.resolve()
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tech = pdk_root / "prtech/techLEF/N551P6M_ecos.lef"
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lef = (
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pdk_root
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/ "IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/lef/"
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"ics55_LLSC_H7CR_ecos.lef"
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)
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required = (args.rtl.resolve(), sdc, pdk_root, tech, lef, liberty)
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missing = [str(path) for path in required if not path.exists()]
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if missing:
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raise FileNotFoundError("missing ECC configuration input(s): " + ", ".join(missing))
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sdc_text = sdc.read_text(encoding="utf-8")
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missing_clocks = [clock for clock in EXPECTED_CLOCKS if f"-name {clock}" not in sdc_text]
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if missing_clocks:
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raise ValueError("ECC SDC is missing clock(s): " + ", ".join(missing_clocks))
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return "\n".join(
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(
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"# Generated by physical/ecc/scripts/generate_config.py; do not edit.",
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"[design]",
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'name = "retrosoc_core"',
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'top = "retrosoc_core"',
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f'rtl = ["{relative(args.rtl, project_dir)}"]',
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'clock_port = "extclk_i_pad"',
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f"frequency_mhz = {args.ext_clk_hz / 1_000_000:.9g}",
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"",
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"[pdk]",
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'name = "ics55"',
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f'root = "{relative(pdk_root, project_dir)}"',
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"",
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"# ECC v0.1.0-alpha.10 resolves PDK content paths relative to pdk.root.",
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"# Supply only the padless H7CR core library and the generated multi-clock SDC.",
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"[pdk.overrides]",
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f'tech = "{relative(tech, pdk_root)}"',
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f'lefs = ["{relative(lef, pdk_root)}"]',
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f'libs = ["{relative(liberty, pdk_root)}"]',
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f'sdc = "{relative(sdc, project_dir)}"',
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'site_core = "core7"',
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'tap_cell = "FILLTAPH7R"',
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'end_cap = "FILLTAPH7R"',
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'fillers = ["FILLER64H7R", "FILLER32H7R", "FILLER16H7R", "FILLER8H7R", "FILLER4H7R", "FILLER2H7R", "FILLER1H7R"]',
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"",
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"[flow]",
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'preset = "harden"',
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'run = "default"',
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"",
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"[params.floorplan]",
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"core_util = 0.60",
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"aspect_ratio = 1.0",
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"",
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"[params.place]",
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"target_density = 0.55",
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"",
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)
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)
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def main() -> int:
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parser = argparse.ArgumentParser(description=__doc__)
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parser.add_argument("--rtl", type=Path, required=True)
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parser.add_argument("--sdc", type=Path, required=True)
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parser.add_argument("--pdk-root", type=Path, required=True)
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parser.add_argument("--h7cr-liberty", type=Path, required=True)
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parser.add_argument("--ext-clk-hz", type=int, required=True)
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parser.add_argument("--output", type=Path, required=True)
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args = parser.parse_args()
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if args.ext_clk_hz <= 0:
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parser.error("--ext-clk-hz must be positive")
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try:
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content = render(args)
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args.output.parent.mkdir(parents=True, exist_ok=True)
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args.output.write_text(content, encoding="utf-8")
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except (OSError, ValueError) as error:
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parser.error(str(error))
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return 0
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if __name__ == "__main__":
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raise SystemExit(main())
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