maksyuki
8ba8a0ad47
- Updated axi4_interconnect_tb to include an additional master and issue high-priority access tests. - Introduced hp_mailbox_tb for testing the HP mailbox functionality, including register and doorbell operations. - Added plic_tb to validate PLIC priority, claim, and completion mechanisms. - Enhanced pll_ctrl_tb to initialize additional system control signals. - Updated soc_irq_topology_tb to account for new IRQ sources and validate IRQ signal behavior. - Improved sysctrl_tb to include tests for HP lifecycle control and status registers. - Added tests for HP boot bundle layout, CRC, and payload validation. - Introduced test_hp_mailbox.py for RTL regression testing of the HP mailbox. - Added test_hp_platform.py to validate HP platform configuration and generated-source boundaries. - Enhanced test_librelane_flow.py to ensure correct signal placement in chip configuration. - Added performance log tests to validate LP and HP coremark ratios. - Updated test_soc_topology.py to reflect changes in IRQ and peripheral mappings.
Reproducible Build Profiles
This directory contains committed Make configuration profiles. Each profile selects SoC, PDK, ISA, CSR support, application, linker layout, and the supported validation tier. The management core is fixed to Hazard3 with its JTAG Debug Module enabled. The user-extension fabric exposes C0-C3 slots for KianV RV32I, SERV, FemtoRV32, and DarkRISCV.
ci/ contains pull-request profiles, cluster/ contains configurations
requiring site tools or PDKs, and benchmark/ contains fixed-workload baseline
profiles. The ihp130-hazard3-coremark.mk profile is the automated SRAM
CoreMark quick measurement; its -standard counterpart is reserved for a
10-second hardware run. The nightly workflow reuses the IHP130 CI profile and
runs the quick CoreMark profile.
ci/ihp130-hp.mk is the experimental asymmetric Linux profile. It fixes both
LP and HP at 72 MHz, runs hp_boot entirely from 32 KiB on-chip SRAM, and
generates VexiiRiscv RTL only below the selected build variant. It is not part
of the supported PR matrix until Linux boot, HP performance, synthesis, and
timing evidence are qualified.
ci/ihp130-xpi-flash-loader.mk builds the SRAM-only XPI NOR service image used
by GDB/OpenOCD; it is a programming utility, not a normal boot application.
Start builds from a committed profile rather than setting an unreviewed mix of
variables on the command line.
SRAM_SIZE_KIB selects 4, 16, 32, 64, or 128 KiB of on-chip SRAM and is part
of the build variant key. IHP130, GF180, and SKY130 CI profiles select eight
4 KiB banks for 32 KiB total and enable both the interface and technology
macro. ICS55 profiles keep the memory absent. IHP130 benchmark and CoreMark
profiles explicitly retain 128 KiB for their fixed workload placement and
SRAM-resident image.
HAVE_SRAM_MACRO=YES requires HAVE_SRAM_IF=YES. The generic manual defaults
enable 32 KiB for IHP130, GF180, and SKY130 and keep ICS55 disabled; committed
profiles remain the supported reproducible entry points.
PDK_BEHAV=YES selects technology-wrapper functional models for behavioral
simulation. It is a simulation-only setting, participates in the build variant
key, and is invalid with Yosys synthesis. Profiles that execute from an SRAM
macro must select either this mode or a qualified macro timing model.
For supported profiles and commands, see the root README and agent contract.