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https://github.com/retroSoC/retroSoC.git
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- Adjusted slot assignments in to reflect new peripheral mappings. - Updated to validate new OpenC906 configurations, including generator and profile checks. - Modified to reference the new Std-series VexiiRiscv generator. - Changed cache maintenance instructions in to align with C906 specifications. - Revised assertions in to account for internal unit removals. - Updated to reflect changes in peripheral interface counts and policies. - Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
16 lines
429 B
Makefile
16 lines
429 B
Makefile
SOC := MINI
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MINI_MODE := PRODUCT
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PDK := ICS55
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HAVE_PLL := NO
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HAVE_SRAM_IF := YES
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HAVE_SRAM_MACRO := YES
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SRAM_SIZE_KIB := 32
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HAVE_HP := YES
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HAVE_SVA := NO
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EXT_CLK_HZ := 72000000
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AUD_CLK_HZ := 18432000
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CLINT_TIMEBASE_HZ := 1000000
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ISA := RV32IM
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HAVE_CSR := NO
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APP := bringup
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LINK_TYPE := ld2_psram
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