mirror of
https://github.com/retroSoC/retroSoC.git
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maksyuki
8d735aafbd
- Adjusted slot assignments in to reflect new peripheral mappings. - Updated to validate new OpenC906 configurations, including generator and profile checks. - Modified to reference the new Std-series VexiiRiscv generator. - Changed cache maintenance instructions in to align with C906 specifications. - Revised assertions in to account for internal unit removals. - Updated to reflect changes in peripheral interface counts and policies. - Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
63 lines
5.3 KiB
Typst
63 lines
5.3 KiB
Typst
#import "../style.typ": *
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#change-start("v05-emphasis-processor-details","Selected body emphasis: processor details")
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#let cpu = data.system_reference.product_details.cpu
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=== Processor Configuration and Software-visible Capabilities <processor-details>
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The table separates the actual LP instance arguments, the fixed HP OpenC906 integration and
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the selected firmware build. It is a *configuration summary*, not a replacement for the CPU
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ISA/CSR manuals. A software compiler option does not remove a hardware extension or CSR block.
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#ds-table("processor-config",[Processor settings and the reference software configuration],
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([Property],[LP: instantiated Hazard3],[HP: locked OpenC906 default configuration]),
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(([Hart / role],[Hart 0; root management.],[Hart #cpu.hp.hartId; application/Linux platform.]),
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([Execution width],[RV32 integration.],[RV64 (#code(cpu.hp_isa_base) base); the core drives 40-bit addresses over a 32-bit physical fabric.]),
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([Configured extensions],cpu.lp_extensions.join(", "),[#cpu.hp_isa.join(", ") (the RV64GC set).]),
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([Privilege],[Machine-mode configuration, U_MODE = #cpu.lp.U_MODE.],[M/S/U per the C906 default configuration; the supplied software platform declares #cpu.hp_mmu.]),
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([Protection],[PMP_REGIONS = #cpu.lp.PMP_REGIONS.],[PMP per the T-Head C906 manuals; entry geometry is not separately extracted in this publication.]),
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([Reset entry],code(data.reset_address),code(cpu.hp.resetVector)),
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([Trap / counter configuration],[MTVEC_INIT: #code(cpu.lp.MTVEC_INIT) \ Machine CSR: #cpu.lp.CSR_M_MANDATORY / counters: #cpu.lp.CSR_COUNTER.],[No memory-mapped mtime; HP software reads the time CSR.]),
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([Debug],[DEBUG_SUPPORT = #cpu.lp.DEBUG_SUPPORT \ Breakpoint triggers: #cpu.lp.BREAKPOINT_TRIGGERS.],[JTAG debug through the core-internal Debug Module and the external DTM; the debug system-bus master is unconnected.]),
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([Bus interfaces],[Use the selected Hazard3 instance and upstream core contract.],[One #(cpu.hp.coreAxiDataWidth)-bit AXI4 master, downsized to the #(cpu.hp.fabricAxiDataWidth)-bit HP fabric; internal CLINT/PLIC window at #code(cpu.hp.sysWindowBase).])),
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widths:(0.8fr,1.6fr,1.75fr))
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The reference LP build uses #code(cpu.build.ISA) with #code("HAVE_CSR="+cpu.build.HAVE_CSR).
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Those build choices are separate from the instantiated LP extension and mandatory CSR settings.
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The HP core is the dependency-locked OpenC906 pre-generated RTL in its default configuration;
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there is no Mini-side generator selection. OpenSBI, the device tree and the kernel
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configuration *must remain consistent with the core that is actually integrated and used*.
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==== Cache geometry and evidence basis
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#ds-table("processor-cache-evidence",[Cache and vendored-core evidence boundaries],
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([Item],[Recorded configuration],[Qualification]),
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(([HP instruction cache],[32 KiB in the default OpenC906 configuration.],[Vendored default configuration; see the qualification note below.]),
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([HP data cache],[32 KiB in the default OpenC906 configuration; 64-byte lines.],[Vendored default configuration; see the qualification note below.]),
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([Cache total capacity],cpu.hp_cache_capacity,[Do not relabel a configured feature as a tested or silicon capability.]),
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([Cache maintenance],[T-Head extended operations (XTheadCmo custom-0 dcache clean/invalidate by address) on 64-byte lines; no Zicbom CBO block.],[Used by the supplied HP smoke image; the extended instruction set must be enabled in the machine status CSR first.]),
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([Locked HP source],[#code(cpu.hp_revision.slice(0,12))],[The full dependency revision is recorded in the lock and publication manifest.]),
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([Vendored HP RTL],cpu.generated_artifact_basis,[The Mini mhartid = #cpu.hp.hartId assignment comes from the reviewed override file, not from editing the vendored checkout.])),
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widths:(0.8fr,1.7fr,1.65fr))
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The vendored OpenC906 checkout is a locked, managed input; the C906 user and integration
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manuals ship with it and remain the register/CSR reference. This publication lists only
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integration-visible settings and does not re-derive upstream implementation parameters.
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==== System window and address decode
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The HP core decodes its internal CLINT/PLIC window at #code(cpu.hp.sysWindowBase) inside the
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core BIU; the matching 128 MiB SoC range is reserved and never reaches the external fabric.
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The reset vector #code(cpu.hp.resetVector) and the 32-bit physical fabric are unchanged by the
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core swap. Per-hart identity is fixed at integration time: the LP Hazard3 reports mhartid 0
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and the HP OpenC906 reports mhartid 1 through the reviewed override.
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Before deploying a new HP image, retain the lock revision, vendored source identity, override
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file and software build identity together. Check the core/device-tree feature agreement and
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the existing non-coherent buffer protocol. LP and HP configuration differences do not turn the
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two harts into a symmetric cache-coherent SMP platform.
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#block(above:rhythm.metadata-before,below:rhythm.metadata-after,breakable:false)[
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#set text(size:9pt)
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#source("rtl/ip/core/mgmt_core_wrapper.sv",title:"LP instance") ·
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#source("rtl/mini/top/hp_core_wrapper.sv",title:"HP OpenC906 integration") ·
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#source("scripts/generate_openc906.py",title:"Vendored filelist and hart-ID override") ·
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#source("app/ports/linux/linux/retrosoc_hp.dts",title:"HP platform properties")
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]
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#change-end("v05-emphasis-processor-details")
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