mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
8d735aafbd
- Adjusted slot assignments in to reflect new peripheral mappings. - Updated to validate new OpenC906 configurations, including generator and profile checks. - Modified to reference the new Std-series VexiiRiscv generator. - Changed cache maintenance instructions in to align with C906 specifications. - Revised assertions in to account for internal unit removals. - Updated to reflect changes in peripheral interface counts and policies. - Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
72 lines
5.0 KiB
Typst
72 lines
5.0 KiB
Typst
#import "../style.typ": *
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#change-start("v05-emphasis-routing-reference","Selected body emphasis: routing reference")
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#let programming = data.system_reference.programming
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== DMA Request, Interrupt and Event Routing <dma-routing>
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Request selectors describe pacing or stream endpoints. Channel numbers describe software
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contexts, and interrupt numbers describe completion delivery. *None can be inferred from another*.
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Central DMA channel conventions are not independent hardware ownership or privilege domains.
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=== Central DMA request map
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#ds-table("dma-request-map",[DMA request numbers checked against RTL, SDK and top-level connections],
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([Request],[Endpoint],[Data transport],[Software channel convention],[Endpoint LP IRQ]),
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programming.dma_routes.map(r=>(str(r.number),r.label,r.transport,r.channel,r.lp_irq)),
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widths:(0.5fr,0.9fr,1.25fr,1.15fr,0.65fr))
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The two SDK XPI selectors map to the RTL's historical QSPI names with identical values.
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UART selectors connect to UART0, not UART1. I2S, DVP and crypto have dedicated stream ports;
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the other paced clients use peripheral data windows through the MM-to-MM path. Software
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selector zero has no dedicated peripheral request wire. WS2812 uses that software-paced path.
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The endpoint IRQ column identifies the peripheral's own event line where one exists; it is
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*not the DMA transfer-completion interrupt*. Central DMA channel events aggregate at the DMA
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resource's LP IRQ or HP external source according to the central resource owner. Crypto has no
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separate LP vector entry in this integration; inspect its register status and DMA completion path.
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=== Software channel allocation
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#ds-table("dma-channel-conventions",[Current SDK and application channel conventions],
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([Channel],[Client / convention],[Basis]),
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programming.channels.map(r=>(str(r.number),r.label,source(r.sources.last(),title:"Driver / allocation source"))),
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widths:(0.5fr,2.7fr,0.9fr))
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The bulk convention is *shared and must be serialized* by the application. XPI accepts an
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explicit channel argument, but selecting another number does not bypass an active stream
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endpoint, resource ownership or buffer-lifetime restriction. Crypto uses separate input/output
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contexts. The HP boot loader uses its declared boot context; channel 7 remains reserved.
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The central DMA start validator currently accepts only its 32-bit width code, even though
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the SDK type also names 8- and 16-bit widths. Streams require a full-word length and the
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supported source/destination increment mode. Do not infer DRE, narrow stream writes, cyclic
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descriptors or 2D operation merely from fields in the descriptor structure.
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=== Private DMA masters and owner-directed completion
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#ds-table("private-dma-routes",[Central and private-master routes with owner-directed interrupts],
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([Engine],[Native master / gateway],[LP vector bit],[HP external source]),
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programming.engines.map(r=>(link(label(r.id),r.name),r.master,str(r.lp_irq),str(r.hp_irq))),
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widths:(1.2fr,1.5fr,0.65fr,0.7fr))
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These HP source numbers are read from the actual SoC interrupt wiring. On the OpenC906
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core-internal PLIC, software addresses each one as *PLIC ID = source + 16*. The Resource Controller
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selects one owner's route and masks routes according to its lifecycle contract; it does not
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deliver a completion to both owners. Private DMA engines do not consume a central DMA channel
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simply because both move memory. They can still share a gateway or destination bandwidth.
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JPEG uses master 6 with one normal read and one normal write credit at class 8;
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this does not establish an end-to-end JPEG system workload.
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JPEG's slot-6 bounded admission and system qualification boundary is described in @bus-programming.
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=== Completion and event handling
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+ Prepare the receiving handler and buffers before enabling the channel, peripheral event and owner route.
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+ On interrupt, identify the aggregate source and inspect the channel/IP event fields; a DMA
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completion does not by itself prove that a serial device finished its on-wire operation.
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+ Check actual length, error and endpoint status, then acknowledge only the documented sticky causes.
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+ Observe each stream's boundary definition. I2S RX has no TLAST, while DVP TLAST marks a line;
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a generic “TLAST means complete frame” rule is incorrect.
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+ On timeout, stop submissions and complete abort/drain before releasing the context or changing ownership.
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The central DMA receiver requires full byte qualification. Odd-pixel DVP lines create a
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partial final stream word and are not supported by its current DMA path. Use the documented
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PIO handling or a separately implemented extension; do not discard the partial-word error.
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#source-note("rtl/ip/peripheral/dma_pkg.sv",title:"RTL request numbers and transfer kinds")
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#source-note("crt/include/retrosoc/hal/dma.h",title:"SDK selectors, contexts and descriptor type")
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#source-note("rtl/mini/top/apb4_periph.sv",title:"Request, stream and PLIC wiring")
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#source-note("rtl/ip/peripheral/dma_core.sv",title:"Start validation, endpoint exclusion and stream acceptance")
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#change-end("v05-emphasis-routing-reference")
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