mirror of
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- Adjusted slot assignments in to reflect new peripheral mappings. - Updated to validate new OpenC906 configurations, including generator and profile checks. - Modified to reference the new Std-series VexiiRiscv generator. - Changed cache maintenance instructions in to align with C906 specifications. - Revised assertions in to account for internal unit removals. - Updated to reflect changes in peripheral interface counts and policies. - Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
142 lines
11 KiB
Typst
142 lines
11 KiB
Typst
#import "../style.typ": *
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#change-start("v05-emphasis-usage-appendices","Selected body emphasis: usage appendices")
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#import "../diagram-packages.typ": storage-figures
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= Appendix: Software Memory and Buffer Requirements <software-memory-budget>
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Memory-map capacity, image allocation, linked image size and peak runtime use are different
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quantities. This appendix supplies source-based layouts and illustrative budgets. No matching
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ELF/MAP files or measured stack/runtime high-water report were available for this update;
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*actual firmware occupation remains unprovided*.
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== Linker Layout and Runtime Accounting
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#ds-table("software-memory-accounting",[Memory quantities and the evidence needed to publish them],
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([Quantity],[How to obtain it],[Current boundary]),
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(([Physical / mapped capacity],[Selected profile and fitted memory/controller geometry.],[The reference SRAM and address map are configuration data, not an application's usage.]),
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([Flash load image],[ELF/MAP LMA, initialized sections and the final packaged image.],[Actual built size not supplied. Do not count NOLOAD BSS as stored bytes.]),
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([Runtime static memory],[VMA for code/rodata/data/BSS in the chosen linker layout.],[Actual section sizes not supplied. Placement differs between SRAM, SDRAM and PSRAM layouts.]),
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([Stack / working space],[Linker constraints plus reviewed worst-case or measured runtime demand.],[A stack-top symbol does not reserve or measure a safe stack budget.]),
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([Boot artifacts],[Loader header allocation bounds and actual package entries.],[Maximum allocations are already listed in the boot chapter; actual image lengths must come from the bundle.]),
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([DMA and media buffers],[Packing, alignment, lifetime, descriptor count and buffer multiplicity.],[The examples below are calculations, *not measured allocations*.])),
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widths:(1fr,1.7fr,1.5fr))
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The all-SRAM script places the main code/rodata/data/BSS in SRAM with initialized content
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loaded from flash. Its #code("_stack_point") is at the SRAM-region end, and #code("_heap_start")
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is a location symbol after static sections. These symbols do not prove an independently bounded
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heap or stack reservation. The freestanding SDK's lack of dynamic allocation does not eliminate
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stack, library scratch or application-buffer requirements.
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The SDRAM and PSRAM linker variants place application material in their named external memory
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regions; inspect the actual script and generated memory regions rather than relying on a
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stale comment or filename. Retain both VMA and LMA in a size report. Compare the sum of static
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sections, reserved buffers and required stack/scratch margin with the available region before boot.
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#change-start("memory-linker-links","Memory accounting links to profile-specific load/run diagrams",category:"cross-reference")
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Profile-specific placement diagrams:
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#("ld2_psram","ld2_all_sram","ld2_sram","jtag_sram").map(name=>
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link(label("storage-linker-"+name),code(name))).join([; ]).
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Each diagram preserves its actual linker regions and selected startup boundary.
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#change-end("memory-linker-links")
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== Worked Buffer Budgets
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The examples use 64-byte allocation alignment for shared HP cache-block ownership. This does
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*not replace the peripheral's minimum alignment*. Each independent buffer receives its own aligned
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stride so a maintenance operation does not include another owner's boundary bytes.
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#storage-figures("software-memory-budget",section:"software")
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#ds-table("buffer-budget-examples",[Payload, stored representation and aligned allocation],
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([Scenario],[Payload / buffer],[Stored / buffer],[Aligned stride],[Total allocation]),
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data.system_reference.programming.budgets.map(r=>(r.name,str(r.payload_bytes),str(r.storage_bytes),str(r.stride_bytes),str(r.total_bytes))),
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widths:(1.65fr,0.65fr,0.65fr,0.65fr,0.75fr),notes:[All numeric entries are bytes. Total includes the stated buffer count.])
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=== DVP RGB565 frame storage
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An even-width RGB565 row has two bytes of effective payload per pixel. The current DVP core
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collects two 16-bit pixels into a 32-bit stream word. For storage planning, use
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#code("row_bytes = ceil(width / 2) * 4") and #code("frame_bytes = row_bytes * height").
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The higher FIFO-side framing metadata is not appended to memory by the central DMA.
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The VGA example therefore uses 614400 bytes per buffer and 1228800 bytes for two buffers.
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This cannot fit in the 32 KiB reference SRAM. Two buffers are an application budgeting example;
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the current DVP convenience interface is a single-frame operation, not automatic hardware ping-pong.
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The 641-pixel example illustrates partial final words and storage rounding. It is not a
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supported central-DMA capture configuration: odd-pixel lines assert partial TKEEP, while the
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DMA receiver requires full words. Use the documented PIO path or a separately implemented
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extension, and allocate explicit software frame metadata where the application needs it.
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=== I2S audio blocks
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For stereo, #code("sample_count = Fs * duration_ms / 1000 * 2"). Require a whole sample-frame
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count. In 16-bit mode two samples occupy one 32-bit word; in 24-bit mode one sample occupies
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one 32-bit word although only 24 bits are payload. A 48 kHz, 10 ms block therefore stores
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1920 bytes in 16-bit mode and 3840 bytes in 24-bit mode. Double buffering requires 3840 and
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7680 bytes respectively with the stated alignment.
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Include application metadata, queue state and scheduling margin separately. The buffer
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duration is not an end-to-end latency guarantee and does not establish tolerance to arbitrary
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memory stalls. I2S RX has no TLAST; the programmed transfer length and software lifetime remain binding.
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=== Descriptor arrays and overflow checks
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Each central DMA TCD occupies 64 bytes and must satisfy its alignment. Eight descriptors
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occupy 512 bytes. This describes a finite descriptor array; it does not imply supported cyclic
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or 2D operation. Account for payload buffers separately from descriptor storage.
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Validate nonzero dimensions, sample count and buffer count before multiplication. Check the
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range before alignment rounding and before multiplying the aligned stride by the number of
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buffers. The publication calculator rejects allocations outside a 32-bit byte range, invalid
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alignment and incomplete audio frames; the application must apply equivalent bounds for its ABI.
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#block(above:rhythm.metadata-before,below:rhythm.metadata-after,breakable:false)[
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#set text(size:9pt)
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#source("crt/linker/ld2_all_sram.lds",title:"SRAM layout") ·
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#source("crt/linker/ld2_sdram.lds",title:"SDRAM layout") ·
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#source("crt/linker/ld2_psram.lds",title:"PSRAM layout") ·
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#source("rtl/ip/multimedia/dvp_core.sv",title:"DVP packing") ·
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#source("crt/src/hal/i2s_math.c",title:"I2S packing")
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]
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= Appendix: Terminology, Notation and Document Map <document-map>
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== Terminology and Units
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#ds-table("system-glossary",[System terminology used in this publication],
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([Term],[Meaning and boundary]),
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data.system_reference.programming.glossary.map(r=>(r.term,r.meaning)),widths:(0.85fr,3.3fr))
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== Reading Numbers and Status
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Register offsets are in bytes; bit ranges name inclusive bit indices. Address-map ranges use
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the stated inclusive end address. Numeric suffixes in signal names denote signal indices,
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not package pin numbers. `_i`, `_o` and `_n` retain their declared direction/polarity meaning.
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An RTL `inout` pad wrapper may contain a functionally input-only route.
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LP interrupt vector bits, HP external sources and their PLIC IDs, DMA request values, software channel contexts
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and native master slots are separate namespaces. A matching integer does not connect them.
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Clock configuration, nominal calculated rate, model timing and characterized pin timing are
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also distinct. Interpret every Min/Typ/Max entry with its stated evidence and conditions.
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"Integrated" and "Partial" describe implementation scope. "Source reviewed", "Tests available"
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and a matching "Reported pass" describe evidence. None silently implies board or silicon
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qualification. Reserved, unsupported and TBD are different states; use the specific meaning
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rather than assuming that an absent value is zero or that an address window guarantees a device.
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== Document and Evidence Navigation
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#change-start("v05-refresh-document-map", "Link the existing task rows to their detailed references", category: "cross-reference")
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#ds-table("document-navigation",[Where to find an authoritative answer],
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([Question],[Primary reference],[How to use this datasheet]),
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(([Addresses, routes and pins],[Canonical memory/topology/pin inputs and generated bindings.],[Use @global-register-index, @dma-routing and @gpio-mux; check @resource-conflicts.]),
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([Register behavior],[Current RTL, handwritten C definitions and reviewed IP contract.],[Use @register-programming and the owning register's exceptions.]),
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([Driver sequence],[SDK implementation, platform source and the IP's software contract.],[Start at @software-support; follow @api-completion and @multicore-operation.]),
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([LP startup / traps],[Selected CRT, linker and conditional IRQ implementation.],[Use @lp-runtime and @irq-runtime; separate pre-main stalls from application results.]),
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([Linux readiness],[OpenSBI, generated DTB and rootfs mailbox publisher.],[Use @linux-runtime; distinguish console, ready event and terminal verdict.]),
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([Diagnostic coverage],[Selected application's actual checks and result branches.],[Use @application-diagnostics and @firmware-application-results; retain stage logs for repeated codes.]),
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([Board connection],[Approved board constraints/schematic and selected device/pad specifications.],[Use @connection-constraints and @device-compatibility for prerequisites and missing evidence.]),
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([Validation or performance],[Matching source/profile report, tool versions, device/model and conditions.],[Use @release-verification and @performance-characterization; source presence is not a pass.]),
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([Publication identity],[This PDF's manifest and matching publication source set.],[Use @publication-provenance for publication-only metadata links.])),
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widths:(0.85fr,1.75fr,1.55fr))
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#change-end("v05-refresh-document-map")
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The datasheet presents the reviewed snapshot for integration. Detailed IP contracts explain
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local behavior; SDK sources show the implemented calling sequence; board guides define a
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particular physical system; result reports establish only the scope actually tested. Where
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an old narrative conflicts with current executable integration, use the current implementation
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and record the discrepancy rather than silently copying the older statement.
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#source-note("publications/datasheets/system-reference.json",title:"Publication content and evidence index")
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#source-note("docs/README.md",title:"Engineering document map")
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#change-end("v05-emphasis-usage-appendices")
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