mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
8d735aafbd
- Adjusted slot assignments in to reflect new peripheral mappings. - Updated to validate new OpenC906 configurations, including generator and profile checks. - Modified to reference the new Std-series VexiiRiscv generator. - Changed cache maintenance instructions in to align with C906 specifications. - Revised assertions in to account for internal unit removals. - Updated to reflect changes in peripheral interface counts and policies. - Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
3871 lines
78 KiB
JSON
3871 lines
78 KiB
JSON
{
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|
"id": "soc-functional",
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"font_size_pt": 9,
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"font_weight": 400,
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"width_mm": 172,
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"height_mm": 231,
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"sources": [
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|
"rtl/ip/multimedia/axi4s_dvp.sv",
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|
"rtl/ip/usb/apb4_usb2.sv",
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|
"rtl/mini/integration/clock_reset_domains.json",
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|
"rtl/mini/integration/soc_topology.json",
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|
"rtl/mini/pin_map/pin_map.json",
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"rtl/mini/top/apb4_periph.sv",
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"rtl/mini/top/apb4_system.sv",
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|
"rtl/mini/top/memory_pad_mux.sv",
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|
"rtl/ip/core/mgmt_debug_wrapper.sv",
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|
"rtl/mini/top/retrosoc.sv",
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|
"rtl/mini/top/soc_clock_reset_subsystem.sv",
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"rtl/mini/top/soc_data_plane.sv"
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],
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"domains": [
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{
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"id": "aon",
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"label": "AON",
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"fill": "#ECEDEF"
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},
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{
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"id": "lp",
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"label": "LP",
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"fill": "#F4EFE4"
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},
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{
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"id": "hp",
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"label": "HP",
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"fill": "#E7EFF6"
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},
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{
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"id": "pclk",
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"label": "PCLK",
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"fill": "#EBF2E8"
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},
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{
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"id": "memory",
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"label": "MEM",
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"fill": "#EEE9F4"
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},
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{
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"id": "jtag",
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"label": "JTAG",
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"fill": "#E7F2F0"
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},
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{
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"id": "audio",
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"label": "AUDIO",
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"fill": "#F7E9E9"
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},
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{
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"id": "dvp",
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"label": "DVP",
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"fill": "#F8EFD9"
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},
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{
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"id": "usb2_ulpi",
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"nodes": [
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{
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"id": "jtag",
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"module": "rst_sync",
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"port": "clk_i",
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"signal": "s_jtag_tck_buf"
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}
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},
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{
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"id": "lp_core",
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"file": "rtl/mini/top/retrosoc.sv",
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"name": "u_core_wrapper",
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"port": "clk_i",
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"signal": "clk_lp_i"
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}
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},
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{
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"id": "debug",
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"clock": {
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"file": "rtl/mini/top/retrosoc.sv",
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"name": "u_core_wrapper",
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"module": "core_wrapper",
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"port": "clk_i",
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"signal": "clk_lp_i"
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}
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},
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{
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"id": "npu",
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"label": "NPU\n64-MAC / 64 KiB",
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"x": 107,
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"y": 27,
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"w": 43,
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"h": 8,
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"domain": "hp",
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"role": "module",
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"ips": [
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"npu"
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],
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"rotate": false,
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"clock": {
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|
"file": "rtl/mini/top/retrosoc.sv",
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"name": "u_apb4_periph",
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|
"module": "apb4_periph",
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|
"port": "clk_hp_i",
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|
"signal": "clk_hp_i"
|
|
}
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|
},
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{
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|
"id": "ahb_bridge",
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"label": "AHB-Lite → AXI32",
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"w": 51,
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"h": 5.551724137931032,
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"rotate": false
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},
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{
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"id": "lp_bus",
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"label": "LP control · AXI32",
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"x": 28,
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"y": 27,
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"w": 51,
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"h": 6,
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"domain": "lp",
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},
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{
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"id": "lp_mem",
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"label": "LP memory · CDC\nAXI32→AXI64",
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"x": 38.0,
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"y": 35.8,
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"w": 31,
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"h": 6.4,
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"domain": "boundary",
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"role": "bridge",
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"rotate": false,
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"compact": true
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},
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{
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"id": "hp_core",
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"label": "OpenC906\nI$ / D$ / FPU / MMU",
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"x": 107,
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"y": 4.793103448275862,
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"w": 43,
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"h": 11.896551724137932,
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"domain": "hp",
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"role": "module",
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"ips": [
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"hp-aclint",
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"hp-plic"
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],
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"rotate": false,
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"clock": {
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"file": "rtl/mini/top/retrosoc.sv",
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|
"name": "u_hp_subsystem",
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|
"module": "hp_subsystem",
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|
"port": "clk_i",
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|
"signal": "clk_hp_core_i"
|
|
}
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|
},
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{
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|
"id": "hp_mmio",
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|
"label": "MMIO gate / CDC\nAXI64→AXI32",
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"x": 113.5,
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"y": 19.09137931034483,
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"w": 30,
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"h": 6.3,
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"domain": "hp",
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"role": "bridge",
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"ips": [],
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"rotate": false,
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"compact": true
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},
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|
{
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|
"id": "hp_bus",
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|
"label": "HP data interconnect · AXI64",
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|
"x": 88,
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"y": 4,
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"w": 10,
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"h": 134,
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"domain": "hp",
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|
"role": "bus",
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"ips": [],
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"rotate": true
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},
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{
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|
"id": "sram",
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|
"label": "SRAM {sram_kib} KiB",
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"x": 107,
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"y": 36,
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"w": 43,
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"h": 5.5,
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"domain": "hp",
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"role": "module",
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"ips": [
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"sram"
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],
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|
"rotate": false,
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|
"clock": {
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|
"file": "rtl/mini/top/retrosoc.sv",
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|
"name": "u_onchip_ram",
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"module": "onchip_ram",
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|
"port": "clk_i",
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|
"signal": "clk_hp_i"
|
|
}
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|
},
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|
{
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|
"id": "monitor",
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|
"label": "Fabric Monitor",
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|
"x": 107,
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"y": 43,
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"w": 43,
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"h": 5.5,
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"domain": "hp",
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"role": "module",
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"ips": [
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"monitor"
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],
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|
"rotate": false,
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|
"clock": {
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|
"file": "rtl/mini/top/retrosoc.sv",
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|
"name": "u_data_plane",
|
|
"module": "soc_data_plane",
|
|
"port": "clk_hp_i",
|
|
"signal": "clk_hp_i"
|
|
}
|
|
},
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|
{
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|
"id": "mem_bridge",
|
|
"label": "AXI64→AXI32\n4 target CDC bridges",
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|
"x": 105,
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|
"y": 53.75,
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|
"w": 37,
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|
"h": 7.5,
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|
"domain": "memory",
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|
"role": "bridge",
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|
"ips": [],
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|
"rotate": false,
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|
"compact": true
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},
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{
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|
"id": "sdram",
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|
"label": "SDRAM Ctrl",
|
|
"x": 120,
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|
"y": 65,
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"w": 30,
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"h": 6,
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|
"domain": "memory",
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|
"role": "module",
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|
"ips": [
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|
"sdram"
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|
],
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|
"rotate": false,
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|
"clock": {
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|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_axi4_sdram",
|
|
"module": "axi4_sdram",
|
|
"port": "clk_i",
|
|
"signal": "clk_mem_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "qpi",
|
|
"label": "QPI PSRAM",
|
|
"x": 120,
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"y": 77,
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|
"w": 30,
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|
"h": 6,
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|
"domain": "memory",
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|
"role": "module",
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"ips": [
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|
"psram"
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|
],
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|
"rotate": false,
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|
"clock": {
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|
"file": "rtl/mini/top/apb4_periph.sv",
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|
"name": "u_apb4_psram",
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|
"module": "apb4_psram",
|
|
"port": "clk_i",
|
|
"signal": "clk_mem_i"
|
|
}
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|
},
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{
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"id": "opi",
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"label": "OPI PSRAM",
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"x": 120,
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"y": 89,
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"w": 30,
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"h": 6,
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"domain": "memory",
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"role": "module",
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"ips": [
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"opipsram"
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],
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"rotate": false,
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"clock": {
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|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"name": "u_apb4_opipsram",
|
|
"module": "apb4_opipsram",
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|
"port": "clk_i",
|
|
"signal": "clk_mem_i"
|
|
}
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|
},
|
|
{
|
|
"id": "xpi",
|
|
"label": "XPI Ctrl",
|
|
"x": 120,
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"y": 101,
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|
"w": 30,
|
|
"h": 6,
|
|
"domain": "memory",
|
|
"role": "module",
|
|
"ips": [
|
|
"xpi"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"name": "u_apb4_xpi",
|
|
"module": "apb4_xpi",
|
|
"port": "clk_i",
|
|
"signal": "clk_mem_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "apu",
|
|
"label": "APU",
|
|
"x": 28,
|
|
"y": 48,
|
|
"w": 29,
|
|
"h": 6,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"apu"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
},
|
|
"parts": [
|
|
{
|
|
"label": "DMA",
|
|
"width": 9,
|
|
"domain": "pclk"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"id": "sdio0",
|
|
"label": "SDIO0",
|
|
"x": 28,
|
|
"y": 57,
|
|
"w": 29,
|
|
"h": 6,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"sdio0"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
},
|
|
"parts": [
|
|
{
|
|
"label": "DMA",
|
|
"width": 9,
|
|
"domain": "pclk"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"id": "usb2",
|
|
"label": "USB2",
|
|
"x": 28,
|
|
"y": 66,
|
|
"w": 29,
|
|
"h": 6,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"usb2"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
},
|
|
"parts": [
|
|
{
|
|
"label": "ULPI",
|
|
"width": 9,
|
|
"domain": "usb2_ulpi",
|
|
"side": "left",
|
|
"clock": {
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"name": "u_ulpi_rst_sync",
|
|
"module": "rst_sync",
|
|
"port": "clk_i",
|
|
"signal": "clk_ulpi_i"
|
|
}
|
|
},
|
|
{
|
|
"label": "DMA",
|
|
"width": 9,
|
|
"domain": "pclk"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"id": "sdio1",
|
|
"label": "SDIO1",
|
|
"x": 28,
|
|
"y": 77,
|
|
"w": 29,
|
|
"h": 6,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"sdio1"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
},
|
|
"parts": [
|
|
{
|
|
"label": "DMA",
|
|
"width": 9,
|
|
"domain": "pclk"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"id": "spisd",
|
|
"label": "SPI-SD",
|
|
"x": 28,
|
|
"y": 87,
|
|
"w": 29,
|
|
"h": 6,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"spisd"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
},
|
|
"parts": [
|
|
{
|
|
"label": "DMA",
|
|
"width": 9,
|
|
"domain": "pclk"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"id": "dma",
|
|
"label": "DMA · 8 ch",
|
|
"x": 28,
|
|
"y": 99,
|
|
"w": 29,
|
|
"h": 6,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"dma"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "jpeg",
|
|
"label": "JPEG",
|
|
"x": 28,
|
|
"y": 110,
|
|
"w": 29,
|
|
"h": 6,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"jpeg"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
},
|
|
"parts": [
|
|
{
|
|
"label": "DMA",
|
|
"width": 9,
|
|
"domain": "pclk"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"id": "ga2d",
|
|
"label": "GA2D",
|
|
"x": 28,
|
|
"y": 121,
|
|
"w": 29,
|
|
"h": 6,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"ga2d"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
},
|
|
"parts": [
|
|
{
|
|
"label": "DMA",
|
|
"width": 9,
|
|
"domain": "pclk"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"id": "ext-h",
|
|
"label": "EXT-H",
|
|
"x": 28,
|
|
"y": 132,
|
|
"w": 29,
|
|
"h": 6,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"ext-h"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_system",
|
|
"module": "apb4_system",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "gwa",
|
|
"label": "HP I/O\nGW A",
|
|
"x": 63.0,
|
|
"y": 49.0,
|
|
"w": 11,
|
|
"h": 23,
|
|
"domain": "pclk",
|
|
"role": "gateway",
|
|
"ips": [],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_io_gateway_a",
|
|
"module": "hp_axi4_mux3",
|
|
"port": "clk_i",
|
|
"signal": "clk_io_i"
|
|
},
|
|
"compact": true
|
|
},
|
|
{
|
|
"id": "gwb",
|
|
"label": "HP I/O\nGW B",
|
|
"x": 63.0,
|
|
"y": 77.0,
|
|
"w": 11,
|
|
"h": 18,
|
|
"domain": "pclk",
|
|
"role": "gateway",
|
|
"ips": [],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_io_gateway_b",
|
|
"module": "hp_axi4_mux3",
|
|
"port": "clk_i",
|
|
"signal": "clk_io_i"
|
|
},
|
|
"compact": true
|
|
},
|
|
{
|
|
"id": "gca",
|
|
"label": "AXI32→AXI64\nCDC",
|
|
"x": 79.0,
|
|
"y": 50.5,
|
|
"w": 6,
|
|
"h": 20,
|
|
"domain": "boundary",
|
|
"role": "bridge",
|
|
"ips": [],
|
|
"rotate": true,
|
|
"compact": true
|
|
},
|
|
{
|
|
"id": "gcb",
|
|
"label": "AXI32→AXI64\nCDC",
|
|
"x": 79.0,
|
|
"y": 76.0,
|
|
"w": 6,
|
|
"h": 20,
|
|
"domain": "boundary",
|
|
"role": "bridge",
|
|
"ips": [],
|
|
"rotate": true,
|
|
"compact": true
|
|
},
|
|
{
|
|
"id": "dma_bridge",
|
|
"label": "AXI32→AXI64\nCDC",
|
|
"x": 63.5,
|
|
"y": 99.30000000000001,
|
|
"w": 21,
|
|
"h": 6.4,
|
|
"domain": "boundary",
|
|
"role": "bridge",
|
|
"ips": [],
|
|
"rotate": false,
|
|
"compact": true
|
|
},
|
|
{
|
|
"id": "jpeg_cdc",
|
|
"label": "AXI64 / CDC",
|
|
"x": 64.5,
|
|
"y": 110.75,
|
|
"w": 19,
|
|
"h": 4.5,
|
|
"domain": "boundary",
|
|
"role": "bridge",
|
|
"ips": [],
|
|
"rotate": false,
|
|
"compact": true
|
|
},
|
|
{
|
|
"id": "ga2d_cdc",
|
|
"label": "AXI64 / CDC",
|
|
"x": 64.5,
|
|
"y": 121.75,
|
|
"w": 19,
|
|
"h": 4.5,
|
|
"domain": "boundary",
|
|
"role": "bridge",
|
|
"ips": [],
|
|
"rotate": false,
|
|
"compact": true
|
|
},
|
|
{
|
|
"id": "ext-h_cdc",
|
|
"label": "AXI64 / CDC",
|
|
"x": 64.5,
|
|
"y": 132.75,
|
|
"w": 19,
|
|
"h": 4.5,
|
|
"domain": "boundary",
|
|
"role": "bridge",
|
|
"ips": [],
|
|
"rotate": false,
|
|
"compact": true
|
|
},
|
|
{
|
|
"id": "clint",
|
|
"label": "LP CLINT",
|
|
"x": 108,
|
|
"y": 111,
|
|
"w": 42,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"clint"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "hp-mailbox",
|
|
"label": "LP / HP Mailbox",
|
|
"x": 108,
|
|
"y": 132,
|
|
"w": 42,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"hp-mailbox"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "periph_bridge",
|
|
"label": "AXI32→APB4\nCDC",
|
|
"x": 69.5,
|
|
"y": 141.8,
|
|
"w": 21,
|
|
"h": 6.4,
|
|
"domain": "boundary",
|
|
"role": "bridge",
|
|
"ips": [],
|
|
"rotate": false,
|
|
"compact": true
|
|
},
|
|
{
|
|
"id": "system_bridge",
|
|
"label": "AXI32→APB4\nCDC",
|
|
"x": 97.5,
|
|
"y": 141.8,
|
|
"w": 21,
|
|
"h": 6.4,
|
|
"domain": "boundary",
|
|
"role": "bridge",
|
|
"ips": [],
|
|
"rotate": false,
|
|
"compact": true
|
|
},
|
|
{
|
|
"id": "periph_bus",
|
|
"label": "APB4 Peripheral",
|
|
"x": 76,
|
|
"y": 151,
|
|
"w": 8,
|
|
"h": 66,
|
|
"domain": "pclk",
|
|
"role": "bus",
|
|
"ips": [],
|
|
"rotate": true
|
|
},
|
|
{
|
|
"id": "system_bus",
|
|
"label": "APB4 System",
|
|
"x": 104,
|
|
"y": 151,
|
|
"w": 8,
|
|
"h": 55,
|
|
"domain": "pclk",
|
|
"role": "bus",
|
|
"ips": [],
|
|
"rotate": true
|
|
},
|
|
{
|
|
"id": "crypto",
|
|
"label": "Crypto",
|
|
"x": 86,
|
|
"y": 184,
|
|
"w": 16,
|
|
"h": 8,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"crypto"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "cfg_left",
|
|
"label": "",
|
|
"x": 60,
|
|
"y": 46,
|
|
"w": 0,
|
|
"h": 94,
|
|
"domain": "pclk",
|
|
"role": "rail",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "cfg_right",
|
|
"label": "",
|
|
"x": 102,
|
|
"y": 110,
|
|
"w": 0,
|
|
"h": 28,
|
|
"domain": "pclk",
|
|
"role": "rail",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "uart0",
|
|
"label": "UART0",
|
|
"x": 28,
|
|
"y": 152,
|
|
"w": 37,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"uart0"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "uart1",
|
|
"label": "UART1",
|
|
"x": 28,
|
|
"y": 158,
|
|
"w": 37,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"uart1"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "i2c0",
|
|
"label": "I2C0",
|
|
"x": 28,
|
|
"y": 164,
|
|
"w": 37,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"i2c"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "i2c1",
|
|
"label": "I2C1",
|
|
"x": 28,
|
|
"y": 170,
|
|
"w": 37,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"i2c"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "tim0",
|
|
"label": "TIM0",
|
|
"x": 28,
|
|
"y": 176,
|
|
"w": 37,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"timer"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "tim1",
|
|
"label": "TIM1",
|
|
"x": 28,
|
|
"y": 182,
|
|
"w": 37,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"timer"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "gpio",
|
|
"label": "GPIO",
|
|
"x": 28,
|
|
"y": 188,
|
|
"w": 37,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"gpio"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "ws2812",
|
|
"label": "WS2812",
|
|
"x": 28,
|
|
"y": 194,
|
|
"w": 37,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"ws2812"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "i2s",
|
|
"label": "I2S FIFO",
|
|
"x": 49,
|
|
"y": 200,
|
|
"w": 16,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"i2s"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "i2s_io",
|
|
"label": "I2S serial",
|
|
"x": 28,
|
|
"y": 200,
|
|
"w": 18,
|
|
"h": 5.5,
|
|
"domain": "audio",
|
|
"role": "module",
|
|
"ips": [],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"name": "u_apb4_i2s",
|
|
"module": "apb4_i2s",
|
|
"port": "clk_aud_i",
|
|
"signal": "clk_aud_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "dvp",
|
|
"label": "DVP FIFO",
|
|
"x": 49,
|
|
"y": 206,
|
|
"w": 16,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"dvp"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "dvp_io",
|
|
"label": "DVP pixel",
|
|
"x": 28,
|
|
"y": 206,
|
|
"w": 18,
|
|
"h": 5.5,
|
|
"domain": "dvp",
|
|
"role": "module",
|
|
"ips": [],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"name": "u_dvp_pclk_rst_sync",
|
|
"module": "rst_sync",
|
|
"port": "clk_i",
|
|
"signal": "s_pclk_sel"
|
|
}
|
|
},
|
|
{
|
|
"id": "sysctrl",
|
|
"label": "SYSCTRL",
|
|
"x": 28,
|
|
"y": 212,
|
|
"w": 37,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"sysctrl"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "archinfo",
|
|
"label": "ARCHINFO",
|
|
"x": 117,
|
|
"y": 152,
|
|
"w": 33,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"archinfo"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_system",
|
|
"module": "apb4_system",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "rng",
|
|
"label": "RNG",
|
|
"x": 117,
|
|
"y": 158,
|
|
"w": 33,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"rng"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_system",
|
|
"module": "apb4_system",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "pwm",
|
|
"label": "PWM",
|
|
"x": 117,
|
|
"y": 164,
|
|
"w": 33,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"pwm"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_system",
|
|
"module": "apb4_system",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "ps2",
|
|
"label": "PS/2",
|
|
"x": 117,
|
|
"y": 170,
|
|
"w": 33,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"ps2"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_system",
|
|
"module": "apb4_system",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "rtc",
|
|
"label": "RTC regs",
|
|
"x": 117,
|
|
"y": 176,
|
|
"w": 33,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"rtc"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_system",
|
|
"module": "apb4_system",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "wdg",
|
|
"label": "WDG regs",
|
|
"x": 117,
|
|
"y": 182,
|
|
"w": 33,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"wdg"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_system",
|
|
"module": "apb4_system",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "crc",
|
|
"label": "CRC",
|
|
"x": 117,
|
|
"y": 188,
|
|
"w": 33,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"crc"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_system",
|
|
"module": "apb4_system",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "ext-l",
|
|
"label": "EXT-L",
|
|
"x": 117,
|
|
"y": 194,
|
|
"w": 33,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"ext-l"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_system",
|
|
"module": "apb4_system",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "resource",
|
|
"label": "Resource Ctrl",
|
|
"x": 117,
|
|
"y": 200,
|
|
"w": 33,
|
|
"h": 5.5,
|
|
"domain": "pclk",
|
|
"role": "module",
|
|
"ips": [
|
|
"resource"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_system",
|
|
"module": "apb4_system",
|
|
"port": "clk_i",
|
|
"signal": "clk_pclk_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "rtc_time",
|
|
"label": "RTC timing",
|
|
"x": 117,
|
|
"y": 209,
|
|
"w": 16,
|
|
"h": 7,
|
|
"domain": "audio",
|
|
"role": "module",
|
|
"ips": [],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/apb4_system.sv",
|
|
"name": "u_rtc_if",
|
|
"module": "rtc_if",
|
|
"port": "rtc_clk_i",
|
|
"signal": "clk_aud_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "wdg_time",
|
|
"label": "WDG timing",
|
|
"x": 134,
|
|
"y": 209,
|
|
"w": 16,
|
|
"h": 7,
|
|
"domain": "audio",
|
|
"role": "module",
|
|
"ips": [],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/apb4_system.sv",
|
|
"name": "u_wdg_if",
|
|
"module": "wdg_if",
|
|
"port": "wdg_clk_i",
|
|
"signal": "clk_aud_i"
|
|
}
|
|
},
|
|
{
|
|
"id": "rcu",
|
|
"label": "RCU · Clock / reset control",
|
|
"x": 28,
|
|
"y": 222,
|
|
"w": 122,
|
|
"h": 7,
|
|
"domain": "aon",
|
|
"role": "module",
|
|
"ips": [
|
|
"rcu"
|
|
],
|
|
"rotate": false,
|
|
"clock": {
|
|
"file": "rtl/mini/top/soc_clock_reset_subsystem.sv",
|
|
"name": "u_aon_rst_sync",
|
|
"module": "rst_sync",
|
|
"port": "clk_i",
|
|
"signal": "s_ref24_clk_buf"
|
|
}
|
|
},
|
|
{
|
|
"id": "jtag_pins",
|
|
"label": "TCK/TMS/TDI\nTDO/TRSTn",
|
|
"x": 1,
|
|
"y": 11.89655172413793,
|
|
"w": 22,
|
|
"h": 8,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "sdio0_pins",
|
|
"label": "CK/CMD/D[3:0]*",
|
|
"x": 1,
|
|
"y": 56.0,
|
|
"w": 23,
|
|
"h": 8,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "sdio1_pins",
|
|
"label": "CK/CMD/D[3:0]",
|
|
"x": 1,
|
|
"y": 76.0,
|
|
"w": 23,
|
|
"h": 8,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "spisd_pins",
|
|
"label": "SCK/CS*\nMOSI/MISO*",
|
|
"x": 1,
|
|
"y": 85.0,
|
|
"w": 23,
|
|
"h": 10,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "usb_pins",
|
|
"label": "ULPI D[7:0]\nCLK/DIR/NXT\nSTP→ext PHY",
|
|
"x": 1,
|
|
"y": 64.0,
|
|
"w": 23,
|
|
"h": 11,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "sdram_pins",
|
|
"label": "DQ[15:0]\nA/BA/controls",
|
|
"x": 152,
|
|
"y": 64.0,
|
|
"w": 19,
|
|
"h": 9,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "serial_pads",
|
|
"label": "QPI / OPI\nshared pads",
|
|
"x": 152,
|
|
"y": 80.0,
|
|
"w": 19,
|
|
"h": 11,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "xpi_pins",
|
|
"label": "CS[3:0]\nSCK / IO[3:0]",
|
|
"x": 152,
|
|
"y": 99.0,
|
|
"w": 19,
|
|
"h": 10,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "uart0_pins",
|
|
"label": "TX/RX; CTS/RTS*",
|
|
"x": 1,
|
|
"y": 151.5,
|
|
"w": 23,
|
|
"h": 6.5,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "uart1_pins",
|
|
"label": "TX / RX",
|
|
"x": 1,
|
|
"y": 157.5,
|
|
"w": 23,
|
|
"h": 6.5,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "i2c0_pins",
|
|
"label": "SCL/SDA*",
|
|
"x": 1,
|
|
"y": 163.5,
|
|
"w": 23,
|
|
"h": 6.5,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "i2c1_pins",
|
|
"label": "SCL/SDA*",
|
|
"x": 1,
|
|
"y": 169.5,
|
|
"w": 23,
|
|
"h": 6.5,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "gpio_pins",
|
|
"label": "GPIO[31:0]",
|
|
"x": 1,
|
|
"y": 187.5,
|
|
"w": 23,
|
|
"h": 6.5,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "ws2812_pins",
|
|
"label": "DOUT*",
|
|
"x": 1,
|
|
"y": 193.5,
|
|
"w": 23,
|
|
"h": 6.5,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "i2s_io_pins",
|
|
"label": "BCLK/WS/SD*",
|
|
"x": 1,
|
|
"y": 199.5,
|
|
"w": 23,
|
|
"h": 6.5,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "dvp_io_pins",
|
|
"label": "PIXCLK/D/sync*",
|
|
"x": 1,
|
|
"y": 205.5,
|
|
"w": 23,
|
|
"h": 6.5,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "pwm_pins",
|
|
"label": "PWM[3:0]*",
|
|
"x": 152,
|
|
"y": 163.5,
|
|
"w": 19,
|
|
"h": 6.5,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "ps2_pins",
|
|
"label": "CLK / DATA*",
|
|
"x": 152,
|
|
"y": 169.5,
|
|
"w": 19,
|
|
"h": 6.5,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
},
|
|
{
|
|
"id": "clock_pins",
|
|
"label": "REF / EXT / AUD\nRESETn",
|
|
"x": 1,
|
|
"y": 220.0,
|
|
"w": 23,
|
|
"h": 10,
|
|
"domain": null,
|
|
"role": "io",
|
|
"ips": [],
|
|
"rotate": false
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"id": "e0",
|
|
"from": "jtag",
|
|
"to": "debug",
|
|
"source_side": "east",
|
|
"target_side": "north",
|
|
"source_position": 0.5179640718562873,
|
|
"target_position": 0.2,
|
|
"via": [
|
|
[
|
|
23,
|
|
"source"
|
|
],
|
|
[
|
|
23,
|
|
0.1
|
|
],
|
|
[
|
|
"target",
|
|
0.1
|
|
]
|
|
],
|
|
"kind": "control",
|
|
"arrow": true
|
|
},
|
|
{
|
|
"id": "e1",
|
|
"from": "debug",
|
|
"to": "lp_core",
|
|
"source_side": "north",
|
|
"target_side": "north",
|
|
"source_position": 0.5,
|
|
"target_position": 0.82,
|
|
"via": [
|
|
[
|
|
"source",
|
|
2
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|
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|
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|
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|
24,
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|
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|
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|
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139
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|
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|
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|
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|
66,
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|
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|
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|
[
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|
66,
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|
140
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|
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|
|
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|
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|
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|
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|
{
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
[
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|
94,
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|
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|
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|
|
[
|
|
94,
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|
138
|
|
]
|
|
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|
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|
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|
},
|
|
{
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|
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|
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|
|
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|
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|
|
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206
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151,
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207
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207
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|
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|
|
"target_position": 0.5,
|
|
"via": [],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e93",
|
|
"from": "usb_pins",
|
|
"to": "usb2",
|
|
"source_side": "east",
|
|
"target_side": "west",
|
|
"source_position": 0.45454545454545453,
|
|
"target_position": 0.5,
|
|
"via": [],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e94",
|
|
"from": "clock_pins",
|
|
"to": "rcu",
|
|
"source_side": "east",
|
|
"target_side": "west",
|
|
"source_position": 0.55,
|
|
"target_position": 0.5,
|
|
"via": [],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e95",
|
|
"from": "uart0_pins",
|
|
"to": "uart0",
|
|
"source_side": "east",
|
|
"target_side": "west",
|
|
"source_position": 0.5,
|
|
"target_position": 0.5,
|
|
"via": [],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e96",
|
|
"from": "uart1_pins",
|
|
"to": "uart1",
|
|
"source_side": "east",
|
|
"target_side": "west",
|
|
"source_position": 0.5,
|
|
"target_position": 0.5,
|
|
"via": [],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e97",
|
|
"from": "i2c0_pins",
|
|
"to": "i2c0",
|
|
"source_side": "east",
|
|
"target_side": "west",
|
|
"source_position": 0.5,
|
|
"target_position": 0.5,
|
|
"via": [],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e98",
|
|
"from": "i2c1_pins",
|
|
"to": "i2c1",
|
|
"source_side": "east",
|
|
"target_side": "west",
|
|
"source_position": 0.5,
|
|
"target_position": 0.5,
|
|
"via": [],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e99",
|
|
"from": "gpio_pins",
|
|
"to": "gpio",
|
|
"source_side": "east",
|
|
"target_side": "west",
|
|
"source_position": 0.5,
|
|
"target_position": 0.5,
|
|
"via": [],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e100",
|
|
"from": "ws2812_pins",
|
|
"to": "ws2812",
|
|
"source_side": "east",
|
|
"target_side": "west",
|
|
"source_position": 0.5,
|
|
"target_position": 0.5,
|
|
"via": [],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e101",
|
|
"from": "i2s_io_pins",
|
|
"to": "i2s_io",
|
|
"source_side": "east",
|
|
"target_side": "west",
|
|
"source_position": 0.5,
|
|
"target_position": 0.5,
|
|
"via": [],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e102",
|
|
"from": "dvp_io_pins",
|
|
"to": "dvp_io",
|
|
"source_side": "east",
|
|
"target_side": "west",
|
|
"source_position": 0.5,
|
|
"target_position": 0.5,
|
|
"via": [],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e103",
|
|
"from": "pwm",
|
|
"to": "pwm_pins",
|
|
"source_side": "east",
|
|
"target_side": "west",
|
|
"source_position": 0.5,
|
|
"target_position": 0.5,
|
|
"via": [],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e104",
|
|
"from": "ps2",
|
|
"to": "ps2_pins",
|
|
"source_side": "east",
|
|
"target_side": "west",
|
|
"source_position": 0.5,
|
|
"target_position": 0.5,
|
|
"via": [],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e105",
|
|
"from": "sdram",
|
|
"to": "sdram_pins",
|
|
"source_side": "east",
|
|
"target_side": "west",
|
|
"source_position": 0.5833333333333334,
|
|
"target_position": 0.5,
|
|
"via": [],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e106",
|
|
"from": "qpi",
|
|
"to": "serial_pads",
|
|
"source_side": "east",
|
|
"target_side": "west",
|
|
"source_position": 0.5,
|
|
"target_position": 0.25,
|
|
"via": [
|
|
[
|
|
151,
|
|
"source"
|
|
],
|
|
[
|
|
151,
|
|
"target"
|
|
]
|
|
],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e107",
|
|
"from": "opi",
|
|
"to": "serial_pads",
|
|
"source_side": "east",
|
|
"target_side": "west",
|
|
"source_position": 0.5,
|
|
"target_position": 0.75,
|
|
"via": [
|
|
[
|
|
151,
|
|
"source"
|
|
],
|
|
[
|
|
151,
|
|
"target"
|
|
]
|
|
],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e108",
|
|
"from": "xpi",
|
|
"to": "xpi_pins",
|
|
"source_side": "east",
|
|
"target_side": "west",
|
|
"source_position": 0.5,
|
|
"target_position": 0.5,
|
|
"via": [],
|
|
"kind": "io",
|
|
"arrow": false
|
|
},
|
|
{
|
|
"id": "e109",
|
|
"from": "dma",
|
|
"to": "apu",
|
|
"source_side": "west",
|
|
"target_side": "south",
|
|
"source_position": 0.8,
|
|
"target_position": 0.2,
|
|
"via": [
|
|
[
|
|
25.7,
|
|
"source"
|
|
],
|
|
[
|
|
25.7,
|
|
56
|
|
],
|
|
[
|
|
"target",
|
|
56
|
|
]
|
|
],
|
|
"kind": "stream",
|
|
"arrow": true,
|
|
"duplex": true
|
|
},
|
|
{
|
|
"id": "e110",
|
|
"from": "apu",
|
|
"to": "i2s",
|
|
"source_side": "east",
|
|
"target_side": "east",
|
|
"source_position": 0.8,
|
|
"target_position": 0.19999999999999896,
|
|
"via": [
|
|
[
|
|
59.5,
|
|
"source"
|
|
],
|
|
[
|
|
59.5,
|
|
150
|
|
],
|
|
[
|
|
68,
|
|
150
|
|
],
|
|
[
|
|
68,
|
|
"target"
|
|
]
|
|
],
|
|
"kind": "stream",
|
|
"arrow": true,
|
|
"duplex": true
|
|
},
|
|
{
|
|
"id": "e111",
|
|
"from": "dvp",
|
|
"to": "dma",
|
|
"source_side": "east",
|
|
"target_side": "south",
|
|
"source_position": 0.800000000000001,
|
|
"target_position": 0.9,
|
|
"via": [
|
|
[
|
|
70,
|
|
"source"
|
|
],
|
|
[
|
|
70,
|
|
150.8
|
|
],
|
|
[
|
|
59,
|
|
150.8
|
|
],
|
|
[
|
|
59,
|
|
107.3
|
|
],
|
|
[
|
|
"target",
|
|
107.3
|
|
]
|
|
],
|
|
"kind": "stream",
|
|
"arrow": true,
|
|
"duplex": false
|
|
}
|
|
],
|
|
"gateways": [
|
|
{
|
|
"id": "gwa",
|
|
"instance": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_io_gateway_a",
|
|
"module": "hp_axi4_mux3"
|
|
},
|
|
"members": {
|
|
"icache": {
|
|
"node": "apu",
|
|
"signal": "apu_axi4"
|
|
},
|
|
"dcache": {
|
|
"node": "sdio0",
|
|
"signal": "sdio0_axi4"
|
|
},
|
|
"mmio": {
|
|
"node": "usb2",
|
|
"signal": "usb2_axi4"
|
|
}
|
|
},
|
|
"bridge": "gca"
|
|
},
|
|
{
|
|
"id": "gwb",
|
|
"instance": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_io_gateway_b",
|
|
"module": "hp_axi4_mux3"
|
|
},
|
|
"members": {
|
|
"dcache": {
|
|
"node": "spisd",
|
|
"signal": "spisd_axi4"
|
|
},
|
|
"mmio": {
|
|
"node": "sdio1",
|
|
"signal": "sdio1_axi4"
|
|
}
|
|
},
|
|
"bridge": "gcb"
|
|
}
|
|
],
|
|
"bridges": [
|
|
{
|
|
"node": "hp_mmio",
|
|
"instance": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_hp_mmio_cdc",
|
|
"module": "axi4_async_bridge"
|
|
},
|
|
"ports": {
|
|
"src_clk_i": "clk_hp_i",
|
|
"dst_clk_i": "clk_lp_i",
|
|
"src_axi4": "u_hp_mmio_gated_axi4_if",
|
|
"dst_axi4": "u_hp_mmio_lp_axi4_if"
|
|
},
|
|
"input_bits": 64,
|
|
"output_bits": 32,
|
|
"output_protocol": "AXI",
|
|
"widths": {
|
|
"input_bits": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_hp_mmio_wide_axi4_if"
|
|
},
|
|
"output_bits": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_hp_mmio_lp_axi4_if"
|
|
}
|
|
}
|
|
},
|
|
{
|
|
"node": "lp_mem",
|
|
"instance": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_lp_data_cdc",
|
|
"module": "axi4_async_bridge"
|
|
},
|
|
"ports": {
|
|
"src_clk_i": "clk_lp_i",
|
|
"dst_clk_i": "clk_hp_i"
|
|
},
|
|
"input_bits": 32,
|
|
"output_bits": 64,
|
|
"output_protocol": "AXI",
|
|
"widths": {
|
|
"input_bits": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_mgmt_data_axi4_if"
|
|
},
|
|
"output_bits": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_hp_mem_axi4_if"
|
|
}
|
|
}
|
|
},
|
|
{
|
|
"node": "gca",
|
|
"instance": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_io_cdc",
|
|
"module": "axi4_async_bridge"
|
|
},
|
|
"ports": {
|
|
"src_clk_i": "clk_io_i",
|
|
"dst_clk_i": "clk_hp_i"
|
|
},
|
|
"input_bits": 32,
|
|
"output_bits": 64,
|
|
"output_protocol": "AXI",
|
|
"widths": {
|
|
"input_bits": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_io_lp_axi4"
|
|
},
|
|
"output_bits": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_master_axi4"
|
|
}
|
|
}
|
|
},
|
|
{
|
|
"node": "gcb",
|
|
"instance": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_io_upsizer",
|
|
"module": "axi4_upsizer_32to64"
|
|
},
|
|
"ports": {
|
|
"clk_i": "clk_hp_i",
|
|
"narrow": "u_io_hp_axi4[master]",
|
|
"wide": "u_master_axi4[master+2]"
|
|
},
|
|
"input_bits": 32,
|
|
"output_bits": 64,
|
|
"output_protocol": "AXI",
|
|
"widths": {
|
|
"input_bits": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_io_lp_axi4"
|
|
},
|
|
"output_bits": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_master_axi4"
|
|
}
|
|
}
|
|
},
|
|
{
|
|
"node": "mem_bridge",
|
|
"instance": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_target_downsizer",
|
|
"module": "axi4_downsizer_64to32"
|
|
},
|
|
"ports": {
|
|
"clk_i": "clk_mem_i",
|
|
"wide": "u_target_mem_axi4[target-1]",
|
|
"narrow": "u_target_mem_narrow_axi4[target-1]"
|
|
},
|
|
"input_bits": 64,
|
|
"output_bits": 32,
|
|
"output_protocol": "AXI",
|
|
"widths": {
|
|
"input_bits": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_data_sram_axi4_if"
|
|
},
|
|
"output_bits": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_data_sdram_axi4_if"
|
|
}
|
|
}
|
|
},
|
|
{
|
|
"node": "periph_bridge",
|
|
"instance": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_cfg_pclk_cdc",
|
|
"module": "axi4_async_bridge"
|
|
},
|
|
"ports": {
|
|
"src_clk_i": "clk_lp_i",
|
|
"dst_clk_i": "clk_pclk_i"
|
|
},
|
|
"input_bits": 32,
|
|
"output_bits": 32,
|
|
"output_protocol": "APB4",
|
|
"widths": {
|
|
"input_bits": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_cfg_pclk_axi4_if"
|
|
},
|
|
"output_bits": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_system_pclk_axi4_if"
|
|
}
|
|
}
|
|
},
|
|
{
|
|
"node": "system_bridge",
|
|
"instance": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_system_pclk_cdc",
|
|
"module": "axi4_async_bridge"
|
|
},
|
|
"ports": {
|
|
"src_clk_i": "clk_lp_i",
|
|
"dst_clk_i": "clk_pclk_i"
|
|
},
|
|
"input_bits": 32,
|
|
"output_bits": 32,
|
|
"output_protocol": "APB4",
|
|
"widths": {
|
|
"input_bits": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_system_pclk_axi4_if"
|
|
},
|
|
"output_bits": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_cfg_pclk_axi4_if"
|
|
}
|
|
}
|
|
},
|
|
{
|
|
"node": "dma_bridge",
|
|
"instance": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_io_cdc",
|
|
"module": "axi4_async_bridge"
|
|
},
|
|
"ports": {
|
|
"src_clk_i": "clk_io_i",
|
|
"dst_clk_i": "clk_hp_i",
|
|
"src_axi4": "u_io_lp_axi4[master]",
|
|
"dst_axi4": "u_io_hp_axi4[master]"
|
|
},
|
|
"input_bits": 32,
|
|
"output_bits": 64,
|
|
"widths": {
|
|
"input_bits": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_io_lp_axi4"
|
|
},
|
|
"output_bits": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_master_axi4"
|
|
}
|
|
}
|
|
},
|
|
{
|
|
"node": "jpeg_cdc",
|
|
"instance": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_jpeg_cdc",
|
|
"module": "axi4_async_bridge"
|
|
},
|
|
"ports": {
|
|
"src_clk_i": "clk_io_i",
|
|
"dst_clk_i": "clk_hp_i",
|
|
"src_axi4": "jpeg_axi4",
|
|
"dst_axi4": "u_jpeg_hp_axi4"
|
|
},
|
|
"input_bits": 64,
|
|
"output_bits": 64,
|
|
"widths": {
|
|
"input_bits": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_jpeg_hp_axi4"
|
|
},
|
|
"output_bits": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_master_axi4"
|
|
}
|
|
}
|
|
},
|
|
{
|
|
"node": "ga2d_cdc",
|
|
"instance": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_ga2d_cdc",
|
|
"module": "axi4_async_bridge"
|
|
},
|
|
"ports": {
|
|
"src_clk_i": "clk_io_i",
|
|
"dst_clk_i": "clk_hp_i",
|
|
"src_axi4": "u_ga2d_gated_axi4",
|
|
"dst_axi4": "u_ga2d_hp_axi4"
|
|
},
|
|
"input_bits": 64,
|
|
"output_bits": 64,
|
|
"widths": {
|
|
"input_bits": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_ga2d_hp_axi4"
|
|
},
|
|
"output_bits": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_master_axi4"
|
|
}
|
|
}
|
|
},
|
|
{
|
|
"node": "ext-h_cdc",
|
|
"instance": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_ext_h_cdc",
|
|
"module": "axi4_async_bridge"
|
|
},
|
|
"ports": {
|
|
"src_clk_i": "clk_io_i",
|
|
"dst_clk_i": "clk_hp_i",
|
|
"src_axi4": "u_ext_h_gated_axi4",
|
|
"dst_axi4": "u_ext_h_hp_axi4"
|
|
},
|
|
"input_bits": 64,
|
|
"output_bits": 64,
|
|
"widths": {
|
|
"input_bits": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_ext_h_hp_axi4"
|
|
},
|
|
"output_bits": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_master_axi4"
|
|
}
|
|
}
|
|
}
|
|
],
|
|
"interfaces": [
|
|
{
|
|
"node": "jtag_pins",
|
|
"source": "rtl/mini/pin_map/pin_map.json",
|
|
"tokens": [
|
|
"jtag_tck_i_pad",
|
|
"jtag_tdo_o_pad"
|
|
]
|
|
},
|
|
{
|
|
"node": "sdio0_pins",
|
|
"source": "rtl/mini/integration/soc_topology.json",
|
|
"tokens": [
|
|
"u_sdio0_if"
|
|
],
|
|
"af_prefix": "u_sdio0_if."
|
|
},
|
|
{
|
|
"node": "sdio1_pins",
|
|
"source": "rtl/mini/pin_map/pin_map.json",
|
|
"tokens": [
|
|
"sdio1_clk_o_pad",
|
|
"sdio1_cmd_io_pad"
|
|
]
|
|
},
|
|
{
|
|
"node": "spisd_pins",
|
|
"source": "rtl/mini/integration/soc_topology.json",
|
|
"tokens": [
|
|
"u_spisd_if"
|
|
],
|
|
"af_prefix": "u_spisd_if."
|
|
},
|
|
{
|
|
"node": "usb_pins",
|
|
"source": "rtl/mini/pin_map/pin_map.json",
|
|
"tokens": [
|
|
"usb2_ulpi_clk_i_pad",
|
|
"usb2_ulpi_stp_o_pad"
|
|
],
|
|
"pin_bus": {
|
|
"prefix": "usb2_ulpi_data",
|
|
"count": 8
|
|
}
|
|
},
|
|
{
|
|
"node": "sdram_pins",
|
|
"source": "rtl/mini/pin_map/pin_map.json",
|
|
"tokens": [
|
|
"sdram_dq",
|
|
"sdram_addr"
|
|
],
|
|
"pin_bus": {
|
|
"prefix": "sdram_dq",
|
|
"count": 16
|
|
}
|
|
},
|
|
{
|
|
"node": "serial_pads",
|
|
"source": "rtl/mini/top/memory_pad_mux.sv",
|
|
"tokens": [
|
|
"controller_qpi",
|
|
"controller_opi"
|
|
]
|
|
},
|
|
{
|
|
"node": "xpi_pins",
|
|
"source": "rtl/mini/pin_map/pin_map.json",
|
|
"tokens": [
|
|
"xpi_nss",
|
|
"xpi_dat"
|
|
],
|
|
"pin_bus": {
|
|
"prefix": "xpi_dat",
|
|
"count": 4
|
|
}
|
|
},
|
|
{
|
|
"node": "uart0_pins",
|
|
"source": "rtl/mini/integration/soc_topology.json",
|
|
"tokens": [
|
|
"u_uart0_if.cts_n_i"
|
|
],
|
|
"af_prefix": "u_uart0_if."
|
|
},
|
|
{
|
|
"node": "uart1_pins",
|
|
"source": "rtl/mini/pin_map/pin_map.json",
|
|
"tokens": [
|
|
"uart1_tx_o_pad",
|
|
"uart1_rx_i_pad"
|
|
]
|
|
},
|
|
{
|
|
"node": "i2c0_pins",
|
|
"source": "rtl/mini/integration/soc_topology.json",
|
|
"tokens": [
|
|
"u_i2c0_if"
|
|
],
|
|
"af_prefix": "u_i2c0_if."
|
|
},
|
|
{
|
|
"node": "i2c1_pins",
|
|
"source": "rtl/mini/integration/soc_topology.json",
|
|
"tokens": [
|
|
"u_i2c1_if"
|
|
],
|
|
"af_prefix": "u_i2c1_if."
|
|
},
|
|
{
|
|
"node": "gpio_pins",
|
|
"source": "rtl/mini/pin_map/pin_map.json",
|
|
"tokens": [
|
|
"gpio_"
|
|
]
|
|
},
|
|
{
|
|
"node": "ws2812_pins",
|
|
"source": "rtl/mini/integration/soc_topology.json",
|
|
"tokens": [
|
|
"u_ws2812_if"
|
|
],
|
|
"af_prefix": "u_ws2812_if."
|
|
},
|
|
{
|
|
"node": "i2s_io_pins",
|
|
"source": "rtl/mini/integration/soc_topology.json",
|
|
"tokens": [
|
|
"u_i2s_if"
|
|
],
|
|
"af_prefix": "u_i2s_if."
|
|
},
|
|
{
|
|
"node": "dvp_io_pins",
|
|
"source": "rtl/mini/integration/soc_topology.json",
|
|
"tokens": [
|
|
"u_dvp_if"
|
|
],
|
|
"af_prefix": "u_dvp_if."
|
|
},
|
|
{
|
|
"node": "pwm_pins",
|
|
"source": "rtl/mini/integration/soc_topology.json",
|
|
"tokens": [
|
|
"u_pwm_if."
|
|
],
|
|
"af_prefix": "u_pwm_if."
|
|
},
|
|
{
|
|
"node": "ps2_pins",
|
|
"source": "rtl/mini/integration/soc_topology.json",
|
|
"tokens": [
|
|
"u_ps2_if."
|
|
],
|
|
"af_prefix": "u_ps2_if."
|
|
},
|
|
{
|
|
"node": "clock_pins",
|
|
"source": "rtl/mini/pin_map/pin_map.json",
|
|
"tokens": [
|
|
"ref24clk_i_pad",
|
|
"extclk_i_pad",
|
|
"audclk_i_pad",
|
|
"ext_rst_n_i_pad"
|
|
]
|
|
}
|
|
],
|
|
"pclk_parent": "lp",
|
|
"masters": [
|
|
{
|
|
"index": 0,
|
|
"name": "hp_mem"
|
|
},
|
|
{
|
|
"index": 1,
|
|
"name": "hp_retired"
|
|
},
|
|
{
|
|
"index": 2,
|
|
"name": "dma"
|
|
},
|
|
{
|
|
"index": 3,
|
|
"name": "io_gateway_a"
|
|
},
|
|
{
|
|
"index": 4,
|
|
"name": "io_gateway_b"
|
|
},
|
|
{
|
|
"index": 5,
|
|
"name": "lp_gateway"
|
|
},
|
|
{
|
|
"index": 6,
|
|
"name": "jpeg"
|
|
},
|
|
{
|
|
"index": 7,
|
|
"name": "ext_h"
|
|
},
|
|
{
|
|
"index": 8,
|
|
"name": "ga2d"
|
|
},
|
|
{
|
|
"index": 9,
|
|
"name": "npu"
|
|
}
|
|
],
|
|
"bus_widths": [
|
|
{
|
|
"node": "lp_bus",
|
|
"bits": 32,
|
|
"interface": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_cfg_pclk_axi4_if"
|
|
}
|
|
},
|
|
{
|
|
"node": "hp_bus",
|
|
"bits": 64,
|
|
"interface": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_master_axi4"
|
|
}
|
|
},
|
|
{
|
|
"node": "ahb_bridge",
|
|
"bits": 32,
|
|
"interface": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_mgmt_data_axi4_if"
|
|
}
|
|
}
|
|
],
|
|
"stream_bindings": [
|
|
{
|
|
"instance": {
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"name": "u_apb4_dma",
|
|
"module": "apb4_dma"
|
|
},
|
|
"ports": {
|
|
"i2s_tx_axis": "u_dma_i2s_tx_axis_if",
|
|
"i2s_rx_axis": "u_dma_i2s_rx_axis_if",
|
|
"dvp_rx_axis": "u_dvp_rx_axis_if",
|
|
"crypto_in_axis": "u_crypto_in_axis_if",
|
|
"crypto_out_axis": "u_crypto_out_axis_if"
|
|
}
|
|
},
|
|
{
|
|
"instance": {
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"name": "u_apb4_apu",
|
|
"module": "apb4_apu"
|
|
},
|
|
"ports": {
|
|
"dma_tx_axis": "u_dma_i2s_tx_axis_if",
|
|
"dma_rx_axis": "u_dma_i2s_rx_axis_if",
|
|
"i2s_tx_axis": "u_i2s_tx_axis_if",
|
|
"i2s_rx_axis": "u_i2s_rx_axis_if"
|
|
}
|
|
},
|
|
{
|
|
"instance": {
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"name": "u_apb4_i2s",
|
|
"module": "apb4_i2s"
|
|
},
|
|
"ports": {
|
|
"tx_axis": "u_i2s_tx_axis_if",
|
|
"rx_axis": "u_i2s_rx_axis_if"
|
|
}
|
|
}
|
|
],
|
|
"typography": {
|
|
"compact_size_pt": 8,
|
|
"emphasis_weight": 700,
|
|
"compact_padding_x_mm": 1,
|
|
"compact_padding_y_mm": 0.6
|
|
},
|
|
"routing": {
|
|
"arrow_length_mm": 1,
|
|
"arrow_width_mm": 0.8,
|
|
"visible_shaft_mm": 1,
|
|
"arrow_clearance_mm": 0.5,
|
|
"stroke_pt": 0.65
|
|
}
|
|
}
|