retroSoC/publications/datasheets/style.md

Mini Datasheet Layout Standard

This document records the implemented layout and maintenance rules of the English retroSoC Mini Gen2/Gen2+ datasheet. The current publication identity belongs in mini.json; release-specific decisions and comparisons belong in the content review and chapter review. This is a maintenance specification, not a new visual design or a hardware specification. The spacing follows the reviewed ST RM0486 Rev 4 reference, adapted to the retained Mini page width and fonts.

style.typ, especially its rhythm configuration, is the executable source of truth for shared typography and spacing. Local behavior is implemented in ip-reference.typ, figures.typ, waveforms.typ and sections/overview.typ. Update this document together with any intentional change to those rules. If documentation and rendering disagree, inspect the implementation and the PDF; do not silently apply an older proposal instead.

Content refresh and evidence rules

Bind each refresh to the complete reviewed dev commit SHA, not a moving branch name or an abbreviated hash. Record when the branch and its CI were checked in UTC; this observation time is separate from the publication date. Recheck before handoff. A later branch advance requires a reviewed source delta before changing the declared snapshot. Preserve unrelated work and the frozen structure, stable anchors and existing layout unless that change is explicitly in scope.

Review every frozen chapter entry against its declared scope. If the current implementation and document are already adequate, state that they are retained and give only a concrete maintenance recommendation. Distinguish a documentation correction, an implementation/specification discrepancy and a missing evidence record. A new version number, more pages or repeated caveats do not improve coverage by themselves. Keep the previous delivered PDF and its digest as the comparison baseline even when the publication version and date are unchanged.

Check the same fact in Features, product/support summaries, tables, detailed prose, code examples and diagrams. Follow the actual configuration, producing branch and lifecycle conditions; a source snippet that still matches is not proof that its surrounding description is current. Update inconsistent summaries with their detailed reference, and retain configuration-dependent and unsupported cases. Do not change RTL, SDK APIs or engineering contracts to fit publication text.

Separate implemented code, default-enabled/advertised capability, available test facilities, executed tests and physical qualification. A successful report needs its complete source SHA, profile, platform/runtime stage, workload, result and original artifact. Distinguish an ordinary Linux path from a freestanding HP acceptance payload even when they use the same mailbox value or log marker. Describe polling budgets in their implemented units and follow every prerequisite through terminal completion; a ready event or early return is not the final pass.

For CI, retain the complete source SHA, UTC observation time, run URL, status, nullable conclusion and job/step scope. Pending, failed prerequisites, skipped downstream tests and completed tests must remain distinguishable. A workflow pass is not an exact-profile IP report; a workflow failure does not prove every runtime stage failed. Prior test counts and narrative summaries are historical until the matching current run and artifacts are reviewed. Never convert a missing corpus, tool or report into a successful execution or physical result.

Use official commercial references to improve organization and clarity. Record document identity, version/revision, release date, check date and relevant sections in the content review, together with the specific organization adopted. Do not transfer product features, electrical limits, performance figures, certification claims or a vendor's release-status policy into Mini. Source/spec discrepancies and missing measurements need explicit follow-up advice, not invented values.

System-use content and evidence

The publication includes a complete system-use reference around the detailed IP chapters. Keep the cover and Overview, then place Product Configuration and Feature Availability and Typical Applications before Reading this datasheet. Contents and the two figure directories follow the complete Product Brief. Memory Attributes/Cache/DMA follows Interconnect; operating-state/reset guidance extends Clock and Reset. Multicore Ownership, Security Boundaries and Debug/Fault Recovery follow Interrupt System and precede Peripherals. Connection constraints extend Packaging. Software owns boot/recovery and the support matrix. Technical Report owns performance methods; Known Limitations precedes Document Control.

Organize system-use topics as capability/prerequisites, key table, normal steps, failure handling and sources. Use native numbered lists for actionable sequences and CeTZ vector diagrams for system connections, state transitions and buffer handoffs. Keep the existing diagram font sizes and palette; label logical flows as ordering rather than measured cycle timing. Do not imply direct IP wiring, new operating modes or a complete application from a conceptual system diagram.

system-reference.json is publication-only metadata for every IP chapter's support row, known limitations and their engineering sources. The builder adds it as data.json.system_reference and hashes all declared sources, tests and report/profile dependencies. Boot-image addresses and bounds are read from the existing loader header; the index does not define or generate RTL, registers or SDK APIs. Keep implementation status separate from verification evidence.

Use Source reviewed, Tests available and Reported pass precisely: a source or test file's existence does not establish a passing run. A reported pass needs the actual report, matching full source revision, profile, platform stage and result. Simulation, FPGA and silicon are different stages. Never promote an old summary, a device-tree node or a published HAL into unqualified platform support. When no matching reviewed report is attached, say so in the matrix and retain physical/performance results as unavailable. A limitation records its impact, trigger, integration response, applicable snapshot and sources.

Publication-only source references lead to Sources and Reproducibility, where the matching release manifest and source set are identified. Do not construct hardware-commit GitHub links for publication files authored after that commit. Engineering and managed-IP references retain their frozen source destinations.

Executable configuration and implementation take precedence over old narrative summaries. Correct stale publication prose and diagrams together; do not change hardware to fit a description. Identify recommended integration policy and pseudocode explicitly. Do not invent callable APIs, cache services, boot retry, ready timeout, authentication, power isolation or silicon qualifications. Keep code examples in the existing syntax-check flow when new C examples are added.

Electrical tables must identify device/process/package, supply/temperature, load/activity and evidence basis. Separate stress ratings, recommended operating conditions, typical observations and guaranteed limits. TBD never means zero. Configuration clocks, behavioral-model checks and analytical bandwidth ceilings are not characterized operating limits or measured system performance. Keep the benchmark profile, workload, placement, measurement boundary and report with any published result; quick CoreMark regression is not a qualified public score.

Cross-IP programming and usage appendices

Bus Transaction Rules and Arbitration belongs inside Interconnect; Clock, Divider and Timebase Programming belongs inside Clock and Reset. Place the DMA Request/Interrupt/Event map after Interrupt System and the coexistence matrix after Multicore Operation. Register Access and Programming Conventions precedes Peripherals. Device Compatibility is a child of External Interfaces. The Software Memory/Buffer and Terminology/Document Map appendices precede Document Control. Keep existing per-IP register details and link to exceptions instead of reproducing them in every global table.

system-reference.json.programming owns reviewed route bindings, channel conventions, conflicts, device-profile evidence and terminology. The publication collector checks RTL/SDK request-number parity (including explicit QSPI/XPI aliases), coverage, actual connection snippets and referenced instances. Channel conventions are supported by driver call sites, not inferred from selector IDs. Private masters and central DMA contexts are different resources. Preserve endpoint IRQ, aggregate DMA IRQ, LP vector bit and HP external source (PLIC ID = source + 16 on the OpenC906 internal PLIC) as separate fields/namespaces. Derive PLIC assignments and normal master credits from the current implementation; mark any connected zero-credit route explicitly.

Cross-IP rules are explanatory defaults with documented exceptions. Do not invent a global atomic-register alias, exclusive-access guarantee or universal multiword read/write order. Describe PSTRB, W1C, FIFO pop, busy-write and dynamic reset behavior at the correct register/instance scope. A value present in an SDK enumeration does not establish that the current hardware start validator accepts it.

Timing examples state input clock, target, integer register values, achieved nominal rate and rounding/error. Cross-check UART/I2C/timer/I2S calculations against the existing pure C helpers, including illegal and boundary inputs. For I2S also check the actual toggle-divider implementation. Nominal digital rates do not qualify board timing or device speed grades. Never substitute STA periods for a peripheral's configured functional input frequency.

Compatibility tables distinguish protocol/geometry, model source/test coverage, board validation and silicon validation. A board/silicon pass needs matching report context, source revision and profile; absent evidence remains explicit. Do not pick an arbitrary commercial part or copy its rated speed into Mini ratings.

Buffer examples state payload packing, word padding, alignment, buffer count and overflow bounds. Distinguish VMA/LMA, static section sizes, image allocation and runtime demand. A linker stack-top or heap-start symbol is not an actual usage measurement. DVP odd-line partial words and I2S 16/24-bit packing must be accounted for; an illustrative double-buffer budget does not imply a hardware ping-pong, cyclic-descriptor or frame-ring capability. Missing ELF/MAP or high-water evidence must remain unprovided, not filled with a calculated maximum allocation.

Validate duplicate/missing routes, number mismatches, missing connections, unknown instances and unsupported qualification claims. Check rounding, field limits, sample packing, alignment and allocation overflow. Host-only C calculation tests do not touch MMIO and are not firmware or hardware measurements. Render all new wide tables, formulas and appendices, check every directory destination, compare unchanged IP engineering data, and repeat the PDF build in an independent directory.

Processor, reset, interface and maintenance detail

Processor Configuration and Software-visible Capabilities follows the LP/HP introductions. Reset-State Summary and Initialization Dependencies extends Clock and Reset. Product Brief includes the interface selection summary, with the full Interface Standards and Supported Subsets matrix before Peripherals. The Multimedia group opens with Data Formats and Peripheral Interoperability before the first actual IP, which still starts on its own page. The labelled multimedia overview closes the previous IP's running-header scope. Image Maintenance belongs after Boot and before the runtime/SDK description.

system-reference.json.product_details records the reset, interface, format, interoperability and physical-evidence summaries. implementation_reference.py reads the named Hazard3 instance, explicit Scala generator assignments, ISA selection, PMA mappings and reference build choices. Reject absent/ambiguous instances, duplicate or missing parameters, unknown IP references and unsupported source bindings. Include all declared dependencies in the publication manifest.

Keep LP instance parameters, HP generator configuration, generated-artifact evidence and software build flags separate. ISA and HAVE_CSR are not a hardware capability inventory. Do not infer cache byte capacity from sets/ways without the reviewed block size or treat a PMA envelope as implemented memory. When the locked upstream checkout/generated manifest is not supplied as publication evidence, identify explicit settings and leave unreviewed defaults/capacities unconfirmed. This is a configuration reference, not a CPU ISA/CSR manual or a new core build.

Reset summaries distinguish asserted reset, assigned initial state and subsequent live observations. Fixed/configured claims need traceable reset assignments or explicit reset-flop parameters plus their primitive semantics. Preserve fixed, configured, input-dependent and dynamic classifications. Resource CONTROL.RESET and controller/global reset are different operations. Initial GPIO control values do not establish physical input voltage, pad pull behavior or package numbering.

Interface tables separate role, source-level subset, exclusions, software support and evidence; none is a compliance certificate. Media tables specify containers, byte order, stride/alignment and boundary metadata. Format compatibility must not override an active integration limitation: JPEG system qualification and APU production-job gates remain visible even for matching data layouts. A claimed format or route must retain its source binding and any blocker reference.

Maintenance commands are operator examples. The publication build never connects a debugger or runs an erase/program operation. Separate script generation from explicit execution and require both executed and passed when interpreting a tool result. A preparation-only pass is not device programming. Describe the actual management-halt/reset scope, SRAM residency, other-master quiescence, sector/readback checks and interruption limits without claiming OTA, A/B, authentication, atomic power-loss updates or rollback. Tests may exercise pure logic and mocked script generation, never real probe/flash operations.

Existing board constraints are identified as board-specific inputs. Missing approved schematics, physical package mappings and characterization reports stay explicitly unprovided in the existing physical/electrical sections. Validate the new scope and result-state distinctions, then build/check/render the full PDF, verify IP preservation and navigation, and repeat the build independently.

Retrieval appendices and release evidence

Place Global Register and Address Index, then Fault and Status Code Reference, after the existing usage appendices and before Document Control. The register index covers every published definition using the existing register records; instance rows may repeat shared definitions without copying the field prose. Sort PRODUCT instances by base/address, then show MPW selections separately. Keep UART/SDIO, timer and I2C instance bases distinct. Separate GPIO user/admin decode coverage, preserve EXT-L/EXT-H capability restrictions, and keep RCU in the SYSCTRL bank. Do not interpret a memory data aperture as a register window.

Retain repeated-bank formulas instead of expanding every channel/array element. Show the element-zero instance-relative offset, first absolute address, stride, valid index range, access and reset meaning. State the 32-bit access width and link each register name to its existing description. Numeric addresses and names use the existing code face; register-name links remain blue without underlines. Long names may break at underscores without changing their visible spelling. Preserve conditional, dynamic and non-retained reset descriptions. Instance overrides require reviewed decoder/parameter bindings. Check the complete expanded address set for overlap and window bounds even though the PDF uses compact rows.

Diagnostic tables identify the producing module and field before the value. Enums, independent mask bits, field positions, application result bytes and simulator strings have separate namespaces. Extract declarations or explicitly selected producing branches and reject omitted/changed codes. Link capture, acknowledgement and recovery semantics back to the owning IP; a code declaration does not establish implemented codec functionality or a usable system route. HP boot codes remain application-scoped. TEST_STATUS validity, sticky completion and simulator success/failure requirements remain distinct from console output.

Packed producer expressions may receive readable field qualifications in the retrieval appendix only with explicit RTL bindings and checked bit ranges. Keep these annotations separate from the existing full register records. Explain requested versus actual lifecycle status, transient completion pulses, rejected writes with observable side effects, and declared SDK masks that the reviewed engine does not emit. Record newly observed source limitations with their scope; do not imply that documenting them fixed or dynamically verified the hardware.

Release Verification Summary belongs in Technical Report. It records source/test availability, exact profile and stage, attached report status, readiness metadata and known limitations. A reported pass requires a real matching report; test-file existence or a successful PDF build is not hardware verification. Preserve the repository readiness declaration without changing its policy or promoting it. Physical release records bind package mapping, circuit/BOM/design assets, parameter conditions, measurement inputs, qualification and ordering identity to their actual device and report revisions. Missing physical data remain unprovided.

Software runtime, diagnostics and frozen structure

Runtime, SDK and Shell owns ordinary LP startup, selected linker/CRT behavior and conditional exception/IRQ support. Distinguish hardware CSRs from HAVE_CSR and CSR_ENABLE, handler registration from enable/acknowledgement, and generic CRT initialization from an APP_CRT_SRCS replacement. Read the selected startup guards as well as linker placement before claiming a wait is present or bypassed. Source loops without a local deadline must remain identified; no new timeout or automatic TEST_STATUS result is implied.

Linux and Driver Status owns the supplied OpenSBI/DT/kernel/rootfs handoff. Separate software template declarations from the generated core and actual clock configuration. Explain the built DTB's patched initrd boundary and the rootfs ready publisher's ordering. Console text, a mailbox event and a hardware terminal result remain separate observations; no native driver or complete boot pass is inferred from a node, callback or source file.

Applications owns the ordered bringup/CI smoke coverage descriptions. Firmware Application Results owns their stage-scoped return/TEST_STATUS meanings and the existing HP boot results. Preserve duplicate code values as distinct application stages, include early C returns, and state destructive scratch/pin/state effects. Controller test-IRQ injection is not CPU ISR delivery or external device traffic. Describe known-answer tests by their actual modes and vectors, not as complete algorithm or physical qualification.

system-reference.json.software contains reviewed source bindings and semantic records. software_reference.py extracts committed startup choices, platform properties, IRQ bounds and actual result-producing branches. Include all source dependencies in the publication manifest. Flow figures describe source ordering with existing vector primitives and fonts; they do not specify cycle timing.

The post-expansion structure-contract.json freezes the outlined level-one and level-two chapter titles, levels, order and existing anchors, plus every actual IP entry even when it is deeper in the hierarchy. Chapter/appendix order and stable destinations must not drift. Level-three and deeper explanatory sections outside the IP-entry set, body text, tables, figures, numbering and pagination remain editable. This is a document organization baseline, not RTL freeze or a promotion beyond the current DRAFT maturity.

Build and PDF check compare the resolved headings with the frozen contract. The renderer exports document-structure.json, which is hashed in the manifest. Normal builds never rewrite the contract. A later explicitly requested structure change must review and update the contract with the corresponding document edit; do not automatically accept a mismatch or introduce a hardware/CI policy gate.

Timeout/completion semantics and boot-bundle byte format

Keep Software Timeouts and Polling Budgets and API Completion and State after Failure inside Runtime, SDK and Shell. The timeout type is not a universal wall-clock unit: record where the reviewed function decrements its budget and what zero means. Separate timer duration from its observation budget. Do not equate a successful command write, FIFO acceptance, completion flag and idle observation. Preserve partial-transfer side effects and the absence of a transferred-length result where the API provides none. State whether timeout only ends observation, requests abort, or attempts stop; never invent rollback.

The representative API table covers the common wait helpers, UART read/write, DMA start/abort/abort-wait/wait and timer delay. Other HALs retain their own contracts. Keep full descriptions centralized and add short links in the selected IP software sections and common register-access guidance. Reviewed function-body digests bind the semantic records; source changes require review instead of silently retaining old conclusions. Digests ignore formatting but preserve string-literal bytes.

HP Boot Bundle Binary Format is a subsection of the existing boot chapter. Tables state byte offsets relative to each structure, word width, little-endian serialization, descriptor-array positioning and the meaning of each size/offset. Distinguish absolute Flash offsets, bundle-relative extent and actual payload length. Header CRC uses a zero CRC field over the complete header/entry area; payload CRC excludes padding. CRC is not authentication or rollback protection.

Always distinguish canonical packager output from the loader's actual checks. Document the larger generated alignment separately from the loader's word alignment, flags-bit tests, reserved-word treatment, range checks and properties that are not independently validated. Do not add stricter software acceptance rules through publication prose. The byte-layout example uses the existing packager with temporary deterministic synthetic files; it is not executable firmware and must never be described as a boot, flash or hardware test result.

system-reference.json.software owns API semantics and bundle-format records. api_bundle_reference.py checks the bindings, extracts fields/constants and verifies the actual synthetic package CRC/layout before publishing values. Use original C function bodies with memory-backed register substitutes for host behavioral checks; no physical MMIO is accessed. Keep the frozen chapter/IP baseline unchanged and rerun the current edit's page-range report.

Modification page-range delivery

For a content edit, retain the immediately preceding delivered PDF as the baseline. Add paired publication-change markers around newly added or substantively changed content and explicit new cross-references. Mark Contents and both figure/table directories separately as navigation updates. Markers are queried after layout; they must not participate in running-header selection.

The build exports and hashes change-markers.json. Generate changed-pages.json with publications/report_changes.py --baseline <previous.pdf> --pdf <final.pdf>. The report verifies both PDF manifest digests, marker integrity, paired in-bounds ranges and the printed footer on each reported page. Preserve baseline/final digests and viewer-page indexes alongside printed page numbers. Check the marked ranges against visible content and a semantic before/after comparison.

The final handoff includes a change-content versus final-page-range table, with added/rewritten content, new cross-references and navigation ranges distinguished. Use printed footer page numbers; also state viewer indexes if they differ.

Separate whole-document presentation changes from content ranges. A repository link replacing the left footer is one global change spanning the delivered page count, not a substantive rewrite of every page. Keep navigation changes and pure page/figure-number shifts distinct. Normalize both old identity footers and new repository footers when comparing retained prose. Describe later pagination/numbering-only changes separately. Update the tracked spans for each new editing round so a prior round's changes are not relabeled as new.

Page, typography and color

Selective emphasis in body content

Use Inter Bold (weight 700) for explicitly selected key phrases, retaining the surrounding font size and color. Emphasize decisive capabilities/parameters, prerequisites, required operation order, restrictions, failure conditions and evidence boundaries. Normally select one to three short spans in a paragraph; do not bold entire paragraphs, tables or every numerical value. Review each chapter rather than applying a global keyword rule.

Handwritten Typst uses *strong spans*. Publication JSON and imported prose use explicit **strong spans** through the IP inline renderer. It preserves emphasis across adjacent text and inline code; backtick code remains opaque, including literal asterisks. This is a limited inline grammar, not executable Typst or a general Markdown interpreter. Preserve code, addresses and register identifiers in regular FiraCode. Avoid unmatched delimiters and verify mixed text/code output.

Heading, table-header and Contents rules remain separate. Do not propagate body emphasis into diagram labels, waveforms, register bit cells or source links. In particular, preserve the 172 mm architecture's regular 8 pt CDC/Gateway, bold 9 pt bus/domain and regular 9 pt remaining labels. Reflow longer bold text without shrinking type. Check representative long tables, section transitions, color/grayscale output and actual embedded Bold glyphs in the resulting PDF.

Base typography

Element	Current rule
Paper	A4 portrait, 210 x 297 mm, including the matrix page
Margins	Left/right 19 mm; top 21 mm; bottom 20 mm
Body area	172 mm wide and 256 mm high
Body	Inter Regular, 10.5 pt, English, left aligned, no first-line indent
Heading levels 1 / 2 / 3 / 4 / 5+	Inter Semibold, 21 / 16 / 13 / 11 / 10.5 pt
Tables, captions, source metadata and header/footer	9 pt
Continuation notices only	Inter Regular, 8.5 pt; renderer-marked size exception
Contents entries	9.5 pt
Signals, addresses and code	FiraCode Nerd Font, 9 pt
Engineering diagram labels	At least 9 pt; only the functional overview's CDC/Gateway labels use 8 pt

The code helper permits line wrapping after underscores and dots using zero-width break opportunities. Do not alter identifiers to make them fit. Preserve the font sizes when content grows; reflow or enlarge the containing layout instead of shrinking the entire figure or page.

Token / purpose	Color
ink: body text, engineering strokes	#292C31
gold: heading numbers, accents and emphasis	#A38442
pale-gold: selected diagram cells and integration notes	#F4EFE4
gray: table headers, code blocks, neutral diagram cells	#F1F2F3
rule: secondary separators and placeholder borders	#D5D6D8
table-stroke: ordinary table frames, row rules and bit-layout grids	Black #000000, 0.6 pt
Figure/table captions and continuation notices	Black #000000
muted: nonlinked metadata, table notes and secondary labels	#62666C
link-color: body links and their underlines	#245A81
inline-code-color: nonlinked Fira Code outside code blocks	#B12146 (RGB 177, 33, 70)

Non-block, nonlinked Fira Code uses inline-code-color in prose, lists, tables and register metadata. This includes identifiers, addresses, offsets, field names and function declarations, through both the code helper and native inline raw text. Keep the existing FiraCode Nerd Font at 9 pt and the current wrap opportunities.

The color matches the inline monospace identifiers and table addresses in the RP2350 datasheet, build date 2025-07-29, printed page 30 (PDF page 31). It was read from the PDF's text color values, not sampled from an antialiased screenshot. Only the color is adopted; no reference-document font or asset is added.

Link color takes precedence: linked Fira Code remains #245A81; body links keep their blue underline, while register-summary name links omit it. The shared inline-code wrapper preserves an inherited link-color scope and applies the red color in other contexts, including muted metadata. Block-level raw code keeps its syntax palette and gray background. Inter paragraphs, register headings and bit-layout labels retain their existing colors.

Color supplements names, labels and line styles. It must not be the only way to read access permissions or distinguish a meaningful engineering state.

Body links use link-color with a same-color 0.4 pt underline, offset 2 pt below the baseline. This applies to external sources and ordinary internal body links. Normal heading cross-references displayed as Section N use the same link-color without an underline. Identify them by their referenced heading, not by matching the rendered words; preserve automatic numbering and the link destination. Register-name links in Register Summary tables are an explicit local exception: keep their blue Fira Code text and destination, without an underline. This does not affect source links beside register descriptions. Underlines follow wrapped text rather than forming one unbreakable line. Source links retain their 9 pt size but do not override link color with muted gray; nonlinked metadata remains muted. The printed navigation directories (Contents, List of tables and List of figures) use ink-colored clickable entries without underlines. Abbreviation emphasis remains confined to Contents.

Shared spacing

All lengths below are points unless another unit is stated. A visual baseline pitch is not the value passed to Typst par(leading:): leading separates text boxes. With the retained Inter font, the relevant box height is approximately 7.639 pt at 10.5 pt and 6.548 pt at 9 pt. Consequently, leading: 4.96pt produces approximately 12.6 pt body baselines, not 4.96 pt baselines. Font changes require measurement in the rendered PDF.

Context	Visual target	rhythm setting / implementation
Body lines	Baseline pitch approximately 12.6	body-leading: 4.96pt
Body paragraphs	Approximately 6.3 extra between paragraphs; last-to-first baseline approximately 18.9	body-spacing: 11.26pt
Small text	Baseline pitch approximately 10.8	small-leading: 4.25pt, small-spacing: 8.25pt
Lists	Body line pitch; approximately 3 extra between ordinary items	list-spacing: 7.96pt, list-indent: 0pt, list-body-indent: 8pt
Figures and numbered tables	12 before and after	figure-space: 12pt
Figure caption	Above the image, separated by 6	figure-caption: 6pt
Table caption	4 from the table	table-caption: 4pt
Continuation notice	8.5 pt type; 2 pt visible space below its text	continuation-size: 8.5pt, continuation-gap: 2pt; internal padding in continuation-notice
Table cells	Horizontal 6, vertical 5 inset	table-inset: (x: 6pt, y: 5pt)
Table notes	6 before the note group	table-notes: 6pt
Code blocks	8 outside before/after, 8 inside	code-space: 8pt, code-inset: 8pt
Notes and placeholders	12 outside before/after, 10 inside	note-space: 12pt, note-inset: 10pt
Standalone source / IP metadata groups	4 before, 6 after	metadata-before: 4pt, metadata-after: 6pt
Register bit layout	6 before/after; one shared boundary between 16-bit halves; horizontal 3, vertical 5 cell inset	bits-space: 6pt, bits-inset: (x: 3pt, y: 5pt)

Fira Code blocks use the small-text leading and 9 pt raw text. Their actual baseline pitch is font-dependent (approximately 10.6 pt in the checked PDF), close to the 10.8 pt small-text target. Do not describe a Typst parameter as an exact measured pitch for every font.

Code-block backgrounds fill 100% of their containing content width, rather than shrinking to the longest code line. In ordinary body flow this is 172 mm; inside a nested list it is the available width after indentation. The 8 pt inset is inside that width. Preserve code font size, syntax coloring, line content and existing wrapping/breakability; never stretch the text to fill the background. Continued code blocks retain the same background width on each page segment.

Headings and flow

Heading	Before	After
Level 1	28	18
Level 2	24	10
Level 3	18	8
Level 4	12	6
Level 5 and deeper	10	5
Functional subheading / minor title	12	6
Register title	12	4

Use heading-layout with one owner for the surrounding margins. Numbered headings have an 8 pt number-to-text gutter and a hanging text column; wrapped lines align with the title text. Functional subheads override spacing without changing the retained size hierarchy. Register identity wrappers own the 12 pt leading margin; their inner heading has zero leading margin and 4 pt trailing margin. Do not add those margins a second time on an enclosing block.

Headings and metadata use sticky blocks to stay with following content. Page-top spacing must not acquire artificial leading blank space. Adjacent block margins can merge; the table above is a component specification, not a requirement to sum all neighboring margins. Verify the rendered transition when nesting blocks.

Use real Typst list and enum elements for features and software procedures. The publication converter preserves nested Markdown lists, wrapped item text, explicit ordered-list numbers and embedded code. Do not substitute paragraphs beginning with a literal dash or number. Continuation lines align with the item text, not its marker.

Navigation and pagination

The entry document requests contents(depth: 5). Preserve this depth and the existing heading hierarchy. Contents starts on a new page after "Reading this datasheet", with its title and first entry together. The front-matter order is Contents -> List of tables -> List of figures -> System Architecture. Each directory starts on a new page and keeps its title with its first entry. Retain the page break after each complete directory and avoid additional blank pages. The two figure-directory titles are unnumbered, excluded from Contents, included as PDF bookmarks, and used as the running header on their pages.

Reading this datasheet links to the existing Terminology, Notation and Document Map appendix. Its existing question-based navigation table links to the relevant internal anchors; keep those destinations meaningful and checked. Improve this single navigation table rather than adding another reader guide or duplicating the detailed reference material. Navigation edits do not change the frozen heading hierarchy or remove deeper PDF bookmarks.

Level-one Contents chapter numbers and complete titles use bold Inter. Dot leaders and page numbers remain regular. Keep the rule local to Contents; body headings, bookmarks and both flat figure/table directories are unaffected. Compose the title separately from the filler/page portion and measure each number column with its actual font weight, including wrapped long titles.

All contents text, including numbering, dot leaders and page numbers, uses the body ink color #292C31, without underlines. This locally overrides ordinary link color and decoration without removing clickable destinations or changing links elsewhere in the document. Within the Peripherals section and its descendants only, uppercase abbreviations inside parentheses are bold. This includes category and multi-IP forms such as (NVM), (OCM / SRAM) and (TIM0, TIM1). Parentheses, separators and qualifiers remain regular: in (APU, partial), only APU is bold. Below level one, titles without parentheses receive no additional emphasis. Apply this formatting to rendered contents entries only, preserving the body headings, bookmark text and technical content.

Deeper functional and register headings remain available through PDF bookmarks and internal links while being excluded from the printed contents. Register summaries link to their detailed descriptions; shared UART/SDIO descriptions use explicit instance-to-common-section links.

Contents entries use approximately 16 pt baselines (toc-leading: 9.09pt), 14 pt indentation per level, and an 8 pt number-to-title gap. The number column is measured from the longest outlined, numbered heading at the same level. Wrapped titles hang under the title text; page numbers remain right aligned with stretching dot leaders. Each entry is unbreakable. Level-one groups add 12 pt before and 4 pt after to the ordinary entry spacing.

The shared figure-directory(tables: false) helper generates List of figures; figure-directory(tables: true) generates List of tables. Follow the single-level layout of RM0486, Rev 4, pages 116 and 134, while retaining the publication's typography. Include every numbered table or non-table figure with a caption, including register tables, native vector diagrams and waveform figures. Read numbers, full captions and actual start-page destinations from the document elements; do not maintain a separate entry list or renumber the body. Include a continued table only once. Unnumbered address tables, bit layouts and decorative components are excluded.

Both directories use Inter 9.5 pt, the approximately 16 pt Contents baseline, and ink-colored clickable entries without underlines. Prefix entries with Table N. or Figure N. and measure one number-column width from the longest prefix in each directory. Use an 8 pt prefix-to-title gap, hanging wrapped titles, stretching dot leaders and right-aligned page numbers. Each whole entry links to the corresponding figure or table start and remains unbreakable. Do not apply Contents hierarchy indentation, chapter-group spacing or abbreviation emphasis to these flat directories. Complete coverage takes precedence over a fixed page budget; allow the directories to grow as numbered material is added.

Outlined, numbered level-one and level-two headings in the body start on a new page, including software, implementation and appendix sections. The entire Product Brief chapter is exempt: Features, Overview, Reading this datasheet and the bottom-aligned first-page note retain their existing flow and explicit breaks. Identify this exception by chapter membership, not chapter number.

A chapter opener and its immediately following first level-two heading share the new page. Do not create a page containing only the level-one title. Later level-two sections start independently, even when their content is short. The shared heading-layout helper applies this rule to body headings, not contents entries, unnumbered detail headings or bookmarks.

Each actual IP still starts on a new page. Keep a category heading with its first IP rather than leaving an isolated category title page. Level-three and deeper headings otherwise retain their existing flow. Automatic chapter/section breaks are weak so they merge with existing breaks at an empty page; never require odd-numbered pages or insert a blank page for a duplicate break. Preserve the explicit page breaks around the matrix figure and its explanatory text, and the independent contents start/end breaks.

Keep figures with their captions, headings with their first content, and short examples with their explanatory notes. Long imported code may break across pages; the minimal SDK example group remains unbreakable. Avoid indiscriminately making a whole IP or long register table unbreakable.

Tables and register pages

Numbered tables use ds-table; their captions remain above the table. Figures and tables have separate numbering. Captions are 9 pt, pure black (#000000) and centered by the figure layout. All figure captions, including Overview, matrix, IP diagrams, waveforms and appendix images, appear above their image with a 6 pt gap. Table captions retain their 4 pt gap. Top captions are sticky and stay with their image or table opening; keep figures unbreakable rather than binding a caption to an unrelated paragraph. Do not add captions to unnumbered images or change figure/table numbering when moving a caption.

Table headers have a light-gray fill and semibold text. Ordinary tables have a complete outer frame and internal horizontal row rules in black (#000000), all 0.6 pt, using the shared table-stroke value. Do not add internal vertical rules. Keep left alignment and vertical centering. The shared table-rules helper supplies the outer cell edges and row boundaries for numbered tables and unnumbered IP address tables. Each continued segment has its own closed frame around the repeated column headers and data rows. Captions, continuation notices and final notes remain outside the frame; the continuation-notice row has only a bottom rule, which forms the top edge of the actual table header below it. All ordinary column headers, including IP address tables and repeated column headers, use gray (#F1F2F3). The bit-number rows in register bit-layout tables remain white; field-name rows retain their existing reserved/field fills. Individual cells cannot split across pages. The helper keeps tables of eight or fewer data rows together and permits larger tables to break. Column headers repeat on continuation pages. Above the repeated column header, show only the exact text (continued), including parentheses, without a caption or table number. A logical table is numbered once. Do not add a repeated bottom caption or silently replace this behavior with a previously proposed footer scheme.

Continuation notices use 8.5 pt Inter Regular in pure black (#000000), aligned left. Keep 2 pt of visible space between the last line of notice text and the table's top rule. Use internal bottom padding rather than collapsible external block spacing. The notice stays with the repeated column header. Regular table captions and other text retain their existing sizes. The caption color applies to both the Figure/Table prefix and its title text. Table notes, waveform explanations, headers/footers and other secondary text retain their existing colors; do not make them black through an enclosing rule.

The continuation-notice helper labels its measured text box. After layout, the build uses typst eval to read the final page and rectangle separately from IP header markers. Do not feed those positions back into the document through a template-wide metadata query, which adds a convergence pass. The build records these markers in layout-regions.json, hashes that file in the PDF manifest, and permits 8.5 pt text only inside those marked regions. Unmarked or partly outside text still requires 9 pt (apart from the separate functional-overview CDC/Gateway exception below), and continuation text below 8.5 pt fails. Missing or changed region data requires rebuilding; do not lower the global font-size threshold to accommodate notices.

Table notes occur once, after the final table segment, in a nonbreaking 9 pt muted block. Inspect their continuity with the table during layout changes. IP address tables and bit-layout tables are unnumbered. IP address tables use the same black 0.6 pt outer frame and horizontal rules and shared 6/5 pt cell insets. Bit-layout tables retain their complete internal grid; CeTZ matrices and other engineering drawings do not inherit ordinary table-frame rules.

Register entries follow this order:

1. Register title, internal anchor and bookmark.
2. Group, offset, access and reset metadata, followed by RTL and C/HAL source links on the next line. Keep this identity group together, in 9 pt small-text rhythm, with 6 pt trailing space.
3. Register description in body typography.
4. One four-row bit-layout table: bits 31:16, their fields, bits 15:0, then their fields. The upper field row and lower bit-number row share one black 0.6 pt rule, with no gap or doubled stroke. Keep the whole component unbreakable and paragraph spacing zero. Use 9 pt labels, the shared 0.6 pt table-stroke, and gray reserved / pale-gold field cells. Both the bit-number and field-name rows have 3 pt horizontal and 5 pt vertical cell insets. Keep the existing total width and 16 columns per segment: extra vertical padding increases row height rather than scaling the text or diagram. Allow the enlarged layout to reflow the document; ordinary field-description tables retain their separate 6/5 pt insets.
5. A numbered field-description table and any register-specific notes.

Long field names use the existing F1, F2, etc. references when they cannot fit a bit span; the field table carries the full name. Do not reduce bit-label font size or change field widths, offsets or semantic data to fit the page.

Cover and engineering figures

Compact first page

The 13 pt positioning line reads exactly: An Open-Source, Linux-Capable Asymmetric Dual-Core SoC.

The cover uses Inter Semibold product lines at 30 and 23 pt, a 13 pt positioning line, and a 9 pt document-status label. Features remain 10.5 pt in two columns with a 7 mm gutter and the existing six groups. This is an explicit compact exception to the ordinary body/list rhythm:

Cover setting	Value
Paragraph leading / spacing	4.96 / 3.675 pt
Level-one / deeper heading before	12 / 12 pt
Heading after	6 pt
General / metadata / rule gaps	3 / 4 / 2 pt
List	Non-tight; cover-list-spacing: 7.96pt; body indent 0.5 em

Features list continuation lines have approximately 12.6 pt baseline spacing, with approximately 3 pt extra between items. Keep all six groups, both columns, 10.5 pt text and the existing group-title styling. Use the elastic space above the Integration Note to accommodate this rhythm, not smaller type or an extra page.

Keep author and author_email separate in the document identity. The cover contact reads exactly Yuchi Miao(miaoyuchi@ict.ac.cn), with no space before the opening parenthesis; the parenthesized address links to mailto:miaoyuchi@ict.ac.cn. PDF author metadata remains Yuchi Miao. Retain the maintenance organization, metadata row alignment and single-page cover.

The prototype brand is Rill（清溪）. Replace the visible RS-MINI-DS in the existing left metadata line with this brand, followed by the regular version text; keep the date on the second line. Retain the document ID in configuration and PDF identity metadata. The running header reads Rill · retroSoC Mini Gen2/Gen2+ at the existing 9 pt size. The main two-line product title is unchanged, and the empty area to its right is reserved for a future logo.

The brand uses 10.5 pt Inter Bold with locked Noto Sans CJK SC Bold 2.004 only for the Chinese/full-width glyphs. Match Inter's 1490/2048 em cap edge explicitly so fallback metrics do not increase the metadata row. Preserve the existing header height, author alignment, date baseline and both horizontal-rule positions. Do not add a brand row or use the logo reservation for text.

The Product Brief heading shares a normal-flow row with an Artifact Evaluation component at the right. Keep the original heading body, numbering, contents entry and bookmark unchanged; the component is separate display content, not a numbered figure or an additional heading.

The outer box is 92 x 10 mm with a 1.5 mm corner radius, a 0.6 pt ink border and white fill (no gray background). Four equal columns show Available, Functional, Reproduced and Tapedout, with 9 pt Inter Regular labels above 3 mm circles. The current explicit artifact-status configuration in sections/overview.typ uses the states full, left-half and empty, not a selected/unselected boolean. Available is fully pale gold (#F4EFE4). Functional has the vertical left semicircle filled in the same pale gold and its right semicircle white; split at the circle center, without an extra divider line. Both retain a complete 0.6 pt gold circular outline. Reproduced and Tapedout remain white with 0.6 pt ink outlines. Use clipped native vector geometry, not a font glyph or raster. The half mark denotes partial functional status, not complete verification or qualification; it does not alter the scoped evidence tables or per-IP results. Keep 4 mm between the heading and box, and vertically center the heading against the box body. The unnumbered 9 pt black label Artifact Evaluation is centered 2 pt below the box. These are native Typst vector shapes and grid content, not a raster asset or a third-party badge image.

Use the cover's elastic space to accommodate the heading row without reducing Features typography or moving content to a second page. Marks are manually maintained publication status; PDF compilation or test success must not automatically select Functional, Reproduced or Tapedout.

The Integration Note uses the shared pale-gold note style, including the 2 pt gold left rule and 10 pt inset. A normal-flow v(1fr) precedes it and its trailing external margin is zero. Its bottom aligns with the first-page body boundary, 20 mm above the sheet bottom. It must not overlap Features or move to page two. Do not achieve this by absolute positioning or shrinking the text.

Specialized diagram packages

Source-bound diagram maintenance

Retain the reviewed IP inventory and its functional, descriptor/parameter, storage, protocol, register and HAL material when it remains accurate. Keep source-level logical storage distinct from a completed technology-macro implementation. Configuration-dependent capabilities and delivery restrictions must agree between diagrams, summaries and the owning IP reference.

Choose a distinct marker prefix for each editing round and record it in the content review and mini.json.change_prefix. The renderer reads that prefix; build/check and change reporting reject markers from earlier rounds. Only the three navigation-directory identifiers may be shared, with navigation status. Activate only the reviewed content and revision markers through current-change. Retained chapters and previous figure work must not be relabeled as newly added. Keep pagination movement separate.

Use the existing Overview icon artwork, including its reverted outline style. The six Multimedia entries use two rows of three cells within the same panel. Keep the repository footer blue and clickable without an underline.

Use namespaced imports through diagram-packages.typ throughout applicable chapters. Circuiteria 0.2.1 covers all 42 IP diagrams plus PRODUCT fabric, clock/reset, media composition and MPW organization. Bytefield 0.0.8 covers source-defined descriptors, bundle headers/entries, serial framing and media/ crypto packing. Rivet 0.3.1 covers APU's common encoding and all seven defined instruction families. Blockcell 0.1.0 covers architectural FIFOs, line buffers, packet/table/control storage, descriptor examples, address windows, linker/load placement and calculated buffer budgets.

Overview classification, the access matrix and software sequence diagrams keep their existing CeTZ rendering. Register descriptions keep the existing bit-layout component and field tables; WaveDrom remains the timing renderer. A register bank, counter or narrative is not by itself a reason to invent an additional FIFO or fixed binary format.

The wrappers render every diagram as Figure, with the existing black 9 pt top caption and figure-directory entry, even when the package internally uses a native table. Keep Inter/Fira Code, gray/gold fills, final type of at least 9 pt, and the current body width. Numeric memory offsets, wire bit order, payload widths and storage capacities must be labeled independently. Address windows are not physical device capacities; diagrams with compressed gaps are not to scale.

Rivet instruction words use upper/lower 32-bit rows so adjacent two-digit bit indexes remain readable. Coordinate and text settings are calibrated together against the rendered PDF; do not solve collisions by making type smaller. Circuiteria boxes use the shared thin-border appearance; its unmodified wire renderer uses 1 pt control/signal lines and 1.5 pt data buses. Dashed control and solid data paths are a local convention. Labels remain horizontal on white backing, with endpoints attached to declared ports. Other diagram line widths are unaffected.

system-reference.json.illustrations references the reviewed circuit, binary layout and storage catalogs. The publication adapters verify named instance bindings and declared signal directions/widths, C member/array offsets, complete field coverage, protocol ordering, FIFO parameters, ranges and selected linker placements. Preserve actual integration overrides, such as DMA's per-channel depth, instead of using a child module's default parameter.

APU opcode values and whole-field zero requirements come from the current encoder/ validator and are checked against RTL. List all 62 defined operations by family; distinguish tool-target acceptance, primitive masks, public capability bits and production delivery. Examples are encoded specimens, not execution/codec-pass evidence. Keep system-qualification boundaries on diagrams, including the distinction between JPEG's bounded master-6 transport (one normal read and one normal write credit at class 8) and an unqualified end-to-end workload. A connected port and admission allocation do not establish a qualified system path.

Every frozen chapter has a coverage record with category, source pointers, primary/shared diagrams or an explicit not-applicable reason. Primary format and storage figures are drawn once; shared instances link to them and retain their own address, routing and capability differences. The build compares this inventory with renderer metadata and rejects missing, duplicate or unknown drawings. Diagram position records support full-size color/grayscale review; they do not feed layout decisions back into the document.

Compressed packet/array diagrams must say they are not to scale and retain every semantic field/range in their data. Show actual word/byte ordering separately from physical wire slots. Linker VMA/LMA figures show placement, not measured usage or proof that a replacement CRT performs relocation/BSS initialization. Budget comparisons do not turn distributed per-row/sample overhead into a fictitious contiguous padding region.

The cache diagram illustrates software-declared 64-byte CBO granules and buffer ownership, not independently verified physical cache tag/set/way organization.

Package identity is the pair of name and version. Rivet/circuiteria's CeTZ 0.3.4 coexists with the existing 0.5.2; oxifmt 0.2.1 likewise coexists with 1.0.0. Circuiteria also requires tidy 0.3.0 at runtime. Validate the complete library import closure from each entrypoint, excluding standalone third-party manuals. Preserve package sources and licenses; prepare them only through the dependency lock and existing setup flow. Normal builds verify caches and never download or rewrite package sources.

Vector diagrams and Overview

Use the locked CeTZ implementation for the retained Overview, access matrix and software workflows. Shared boxes have 0.6 pt ink borders and a 0.6 mm radius; directed wires are 0.65 pt, with solid or dashed lines as appropriate. Coordinates in figures.typ are centimeters at final size. Diagram labels retain diagram-leading: 0.4em; Overview IP labels use inventory-leading: 0.35em. These are deliberate local rules, not body paragraph spacing.

The PRODUCT Overview uses a 172 x 164 mm outer rectangle with a 2 mm radius and 0.85 pt ink border. Its title is 12 pt semibold, with a short gold line, a subtle separator and category icons. Side padding is 4 mm; category gaps are 3 mm. The top and middle rows have three equal-width panels, each 40 mm high. The 55 mm lower area places Connectivity across two columns, with Multimedia and Security and Integrity stacked at the right (29 and 23 mm, separated by 3 mm).

Category titles are 9.5 pt semibold on pale gold. Panels have 0.55 pt muted borders and 1 mm radii. IP cells have 0.5 pt muted borders, 1 mm radii and gray fill; the two processor cells are pale gold. Cells adapt to the item count: Connectivity uses three columns and splits its last row between two items.

overview-groups.json is the sole source of category and IP names (currently nine categories and 45 labels). Show each integrated PRODUCT IP once, without external chips, reserved windows, MPW-only blocks, topology arrows, capacities, frequencies or state badges. Decorative icons express category only. Keep Overview-only drawing helpers separate from shared boxes.

The Interconnect Matrix remains on a portrait page, 172 mm wide: a 45 mm initiator column and five 25.4 mm target columns. Header height is 8.5 mm; the data rows, one per reviewed initiator (currently ten), are 8.2 mm high. Labels stay at least 9 pt. Permissions are printed as R / W, R, W or -; cells allowing writes also use pale gold. Do not rescale the complete drawing or change data to make it fit.

Waveforms

waveforms.typ renders the locked wavy/jogs output as vector SVG, normalizes its typography to Inter, and keeps diagram text and edges dark. Signal names and text inside multibit data blocks use Inter Regular (explicit SVG weight 400), never bold, and remain at least 9 pt at final size. This includes bus values, addresses and protocol-phase labels. Normalize the base SVG text weight as well as the signal-name style in the local renderer wrapper; do not edit the locked third-party renderer. Preserve data-label text, size, color and waveform geometry. Lane names must be lowercase real port, interface member or internal-signal names; retain _i, _o, _n and verified bit/array selections. Do not turn a prose event such as "memory fence" into a fictitious signal by replacing spaces with underscores.

waveforms.json owns both the WaveDrom source and each lane's signals provenance record: RTL file, module/interface scope, declared symbol, polarity and meaning. Each figure records its clock_domain, review_note and review_sources; parameter overrides require a parameter_note. The visible note identifies the scopes and clock domain. Software actions and compressed protocol phases belong in that explanation or in data-value labels, not lane names. Data labels keep their protocol meaning and are not mechanically lowercased.

waveform_reference.py checks one-to-one lane/source coverage, declaration presence in the correct scope, lowercase names, parameter resolution, array/bit bounds and scalar-versus-bus notation. Comments and names from unrelated modules do not establish a declaration. This bounded checker does not elaborate arbitrary SystemVerilog or simulate behavior; the stored behavior review supplies the semantic qualification. Unsupported declaration forms require an explicit, tested parser extension rather than a silent bypass. All source/review files enter the publication input hash. Each build emits waveform-audit.json with resolved widths, declaration lines and review notes.

Retain a trajectory only when it expresses the real signal's behavior. Split combined address/data lanes and distinguish sampled inputs, driven outputs and output enables. Move unmappable behavior rows into prose or replace them with a reviewed transaction. Omitted intervals and example parameters must be explicit; never present a schematic waveform as measured latency or electrical signoff. Long names must fit without reducing text below 9 pt; adjust the label area or split a dense example when necessary.

Each figure's multi-bit signal rows receive these valid-data fills in order, including rows inside nested signal groups:

Sequence	Fill
1	Pale gold #F4EFE4
2	Blue gray #E7EFF6
3	Green gray #E8F1EA
4	Purple gray #EEEAF5

Cycle after four rows and restart at each figure. All valid data segments of a row use its assigned color. Modify only the rendering copy's valid bus color codes (=, 2 through 9); keep the canonical WaveDrom data unchanged. Clocks, single-bit signals, unknown-state patterns, high impedance, edge positions, labels, nodes and connections retain their meaning and geometry.

The top caption, waveform and bottom explanatory note form one nonbreaking group spanning the full body width with 12 pt before/after. The note is center-aligned within that width, uses 9 pt muted small-text rhythm and 4 pt leading space. Keep outer figure spacing on the group only. Inspect the actual SVG as well as color and grayscale PDF renders.

Header, footer, assets and maintenance

Compact PRODUCT functional architecture

Insert the new cetz:soc-functional figure after the Section 2.1.1 introduction. It is a single portrait vector diagram within the 172 mm body width; keep its caption and diagram together and allow normal pagination if the current page is too short. Use locked CeTZ 0.5.2 directly. This component does not replace or restyle existing Circuiteria/IP, interconnect, clock, Overview or matrix figures.

Use Inter with these scoped rules: ordinary IP, external-interface and explanatory labels are Regular 400 at 9 pt; CDC and HP I/O Gateway labels are Regular 400 at 8 pt; the four gray bus spines, clock-domain titles and domain-key names are Bold 700 at 9 pt. Non-CDC bridges retain ordinary 9 pt type. The 8 pt exception is exclusive to the approved compact cells in this figure and does not lower any other diagram's minimum. Semibold is not a substitute for Bold.

Size CDC rectangles and Gateway A/B trapezoids from the compact labels, with 1 mm horizontal and 0.6 mm vertical text padding. Both dimensions must be smaller than the preceding 9 pt drawing, while the gateways retain separate input ports. Compact text uses 1 pt leading. Keep thin 0.6 pt symbol borders, 0.65 pt routes, pale domain backgrounds and the existing ink/gold palette. Rotate long bus-spine and narrow bridge labels by 90 degrees where needed; keep ordinary module and external-interface labels horizontal.

Use only horizontal/vertical connector centerlines. Arrow flanks and gateway outlines may be diagonal. Arrowheads are 1 mm long and 0.8 mm wide; reserve at least 1 mm of straight shaft beyond each head (3 mm total for a straight duplex gap). Other routes must remain at least 0.5 mm outside an arrowhead's stroke envelope. Avoid unrelated symbols and exported text, including domain titles. Ordinary crossings without junctions remain unconnected. Draw from the same computed route/head geometry used by the validator, rather than independent renderer defaults. CDC ingress and egress lines must remain visible.

Check actual PDF typography using renderer-bound positions recorded and hashed in layout-regions.json. Only named CDC/Gateway regions authorize 8 pt. The final check requires exact 8/9 pt sizes and 400/700 weights by role; it rejects text outside its exception, empty/overlapping regions and line/text collisions. For quarter-turn labels use the rendered width as the font-height axis, since PDFMiner's size then measures glyph advance. Embedded variable-font subsets can retain the name Inter-Regular and omit OS/2 weight metadata; compare retained glyph outlines with locked Inter instances at weights 400 and 700 instead.

CPU and memory blocks occupy the top tier, independent initiators and gateways the middle, and narrow APB peripheral rows the lower tier. Name UART0/1, I2C0/1, TIM0/1 and SDIO0/1 individually. Cover every PRODUCT IP; the separate MPW IPs remain in their appendix. Show DMA subcells only for implementations with the corresponding private path, and keep the central eight-channel DMA independent of Gateway A/B. Avoid summary boxes that collapse several unrelated peripherals or a large Reference panel that displaces functional content. Below the figure, use top-aligned columns of 64 mm and 102 mm with a 6 mm gap and no outer frame. The left column holds the nine existing domain colors in a three-column, three-row key; the right preserves the existing gateway, arrow, LP/PCLK, AF, shared-pad and crossing explanations, wrapped at 9 pt.

AXI32/AXI64 text is permitted only in bus-spine and bridge symbols. It must not reappear in CPU/IP titles or as floating wire labels. Identify AHB-Lite to AXI, MMIO gating/downsizing, ingress CDC/upsizing and four independent memory-target CDC/downsizing paths in their bridge symbols. APB4 and stream paths stay distinct. Gateway A visibly receives separate APU, SDIO0 and USB2 inputs; Gateway B receives separate SDIO1 and SPI-SD inputs. Each has one output to its own CDC/width bridge and then the HP fabric. The two outputs are not merged into one fabricated bus.

Use the following functional clock-domain fills, with printed names or a compact key. Multi-clock peripherals have distinct control/FIFO and timing/link views.

Domain	Fill
AON	#ECEDEF
LP	#F4EFE4
HP	#E7EFF6
PCLK	#EBF2E8
MEM	#EEE9F4
JTAG	#E7F2F0
AUDIO	#F7E9E9
DVP	#F8EFD9
ULPI	#E8ECF7

Both APB4 register islands are PCLK functions. SRAM and Fabric Monitor execute in HP; NPU computation, private SRAM and payload DMA also execute in HP, while its PCLK control CDC is expanded in the NPU chapter. Its overview node must lie inside an HP background and bind the NPU chapter identity. The external-memory controllers execute in MEM. PCLK derives from LP, so different fills do not imply all domain pairs are asynchronous. These are functional clock regions, not power islands or timing-signoff statements.

Place concise external signal groups outside the module rows. Bind them to the pin map, interface declarations or actual GPIO alternate-function routes. Mark GPIO alternate functions, QPI/OPI shared-pad selection and the external ULPI PHY accurately; interface arrows do not promise concurrent use of conflicting routes. Solid request paths and grey stream paths remain visually distinct; responses and remote register-control CDC detail may be omitted from this overview and retained in the detailed references. Crossings without junctions are not joins.

The catalog records semantic node roles, clock sources, gateway inputs/output, literal interface widths, stream connections, source files and external pin groups. Validate those against current sources and include them in the manifest. Record the CeTZ category in the 109-entry coverage report and require the actual render. The reviewed specialized inventory has 142 figures, including the NPU circuit, descriptor/parameter layouts and storage views. Preserve the existing package renderers and use source-bound content for every changed figure.

Independent closing page

Append one unnumbered closing page after Document Status and Contact. It is an A4 page with 19 mm left/right margins and a 24 mm bottom margin; hide its running header, footer, rules, date and visible page number in a local page scope. Count it in the full PDF total. It has no heading, bookmark, figure number or directory entry, so it remains outside the 42-IP / 109-entry structure contract.

Bottom-align a single nonbreaking content block. Its first element is an empty 60 x 14 mm white rectangle with a 0.6 pt gold outline, reserved for a future logo. Do not add a label, caption, placeholder text or an external logo asset. Leave 7 mm before the 13 pt Inter Semibold title, "Disclaimer and Copyright Notice". Use 9 pt Inter Regular text with the small-text leading (about 10.8 pt baseline pitch) and 5 pt paragraph spacing. Keep the existing ink/gold/link palette.

Use the reviewed English notice in sections/closing.typ, the copyright line from the project LICENSE and a blue clickable repository link. The notice refers to Mulan PSL v2 and third-party licenses without substituting new license terms or importing another manufacturer's copyright/trademark statements.

The start/end metadata must identify one complete final page. Export page-roles.json and bind its digest in the manifest. Only that validated role permits absent footer content and links; all ordinary pages remain subject to the standard furniture checks. Missing, modified, duplicated or non-final role records fail validation. Change reports use viewer indexes and null printed page values for this page. Keep first-page Integration note placement intact.

Running furniture and managed assets

The header displays retroSoC Mini Gen2/Gen2+ from doc.title on the left and the active IP identifier, or current level-one chapter outside an IP, on the right. It uses 9 pt muted text, a 4 pt gap and a 0.6 pt gold rule. The footer uses a 0.35 pt separator, a 4 pt gap and 9 pt Inter. At left, display the complete single-line URL https://github.com/retroSoC/retroSoC, linked to that exact destination with the existing blue link color, without an underline. Apply this decoration exception locally to the footer repository link; other source links retain their existing underlines. Keep current/total page count centered and the document date right-aligned in muted text. Document ID/version/status remain on the cover, in Document Control and in PDF metadata. Identity values come from mini.json; do not duplicate them in layout helpers or add a watermark.

Fonts, font licenses and static assets remain in the independently managed, ignored publications/media/ repository. Editable engineering drawings remain Typst source. The shared dependency lock owns media and package revisions, including CeTZ, wavy and jogs. Retain Typst 0.15.1 and the existing manual publication workflow; do not add root Makefile targets, downloads, assets or package dependencies for a spacing adjustment.

Run the documented commands from the repository root:

python publications/build_datasheet.py setup
python publications/build_datasheet.py build
python publications/build_datasheet.py check
git diff --check

Setup is needed to prepare locked resources; ordinary builds use the prepared resources offline. Pass --typst PATH to setup/build when needed. See the publication guide for output paths, reproducibility, dependency checks and validation requirements when Python or technical inputs change.

For layout changes, render the whole PDF and inspect the cover, contents, long titles, nested lists, continued tables, dense registers, code, Overview and matrix at final size and in grayscale. Verify font embedding, links, bookmarks, IP starts, clipping and the cover-note position. Measure baseline pitches after font or spacing changes. Confirm technical text and generated data are unchanged for a style-only change, and verify byte-identical offline repeat builds.

For figure-directory changes, verify one-to-one coverage against numbered body captions, with no duplicates or omitted entries. Check each displayed page and link destination against the body start page, including continued tables. Inspect both directories' first, intermediate and final pages, long captions, four-digit table numbers and the transition to System Architecture. Confirm that body caption numbers and text are unchanged, new titles do not appear in Contents, bookmarks and running headers are correct, and Contents links and footer page totals reflect the added pages.

For heading-link or waveform-weight changes, verify that every normal heading reference is blue, has no underline and still reaches its original heading. Sample ordinary source links and all three navigation directories for style isolation. Export every waveform and inspect the effective font weight of signal names and multibit data labels, including inherited SVG text styles. Render short, long and successive bus labels at final size to check for overlap or clipping. Confirm technical text, figure numbering and generated data are unchanged.

For system-use additions, check the support inventory against every IP chapter, reject duplicate/missing identifiers and broken source paths, and test rejection of verification claims without the required report context. Verify boot-layout extraction and dependency hashing. Review every new engineering statement against its source; compare the existing hardware/register data before and after the change. New chapter/table/figure numbers may change automatically, but labels, destinations and existing technical content must remain valid. Render the full PDF, inspect new tables/flows and chapter transitions, and verify a byte-identical offline repeat build in a separate output directory. Do not replace missing hardware evidence with a successful publication build.

For an edit confined to this Markdown specification or its README link, verify the descriptions, relative links and commands and run git diff --check; rebuilding the PDF and running hardware validation are not required.