mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
8d735aafbd
- Adjusted slot assignments in to reflect new peripheral mappings. - Updated to validate new OpenC906 configurations, including generator and profile checks. - Modified to reference the new Std-series VexiiRiscv generator. - Changed cache maintenance instructions in to align with C906 specifications. - Revised assertions in to account for internal unit removals. - Updated to reflect changes in peripheral interface counts and policies. - Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
204 lines
6.3 KiB
Verilog
204 lines
6.3 KiB
Verilog
// retroSoC controlled override of the vendored OpenC906 aq_sysio_kid.v.
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//
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// Source: openc906 dependency (dependencies.lock.json "openc906"),
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// C906_RTL_FACTORY/gen_rtl/cpu/rtl/aq_sysio_kid.v
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// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f
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// License: Apache-2.0 (T-Head Semiconductor)
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//
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// retroSoC change (Mini LP/HP contract): the HP core must report mhartid=1
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// (the LP Hazard3 core is hart 0). Upstream hardwires sysio_core_hartid to
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// 3'b0 and exposes no top-level hart-id port, so this file substitutes the
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// vendored module with sysio_core_hartid = 3'd1. Everything else is
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// byte-identical to upstream. Keep in sync when the lock revision changes.
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module aq_sysio_kid(
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apb_clk_en,
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axim_clk_en,
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clint_core_ms_int,
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clint_core_mt_int,
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clint_core_ss_int,
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clint_core_st_int,
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core_pad_lpmd_b,
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core_sysio_lpmd_b,
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cpurst_b,
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forever_cpuclk,
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pad_yy_icg_scan_en,
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plic_core_me_int,
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plic_core_se_int,
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sysio_core_hartid,
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sysio_core_me_int,
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sysio_core_ms_int,
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sysio_core_mt_int,
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sysio_core_se_int,
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sysio_core_ss_int,
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sysio_core_st_int
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);
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// &Ports; @23
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input apb_clk_en;
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input axim_clk_en;
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input clint_core_ms_int;
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input clint_core_mt_int;
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input clint_core_ss_int;
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input clint_core_st_int;
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input [1:0] core_sysio_lpmd_b;
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input cpurst_b;
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input forever_cpuclk;
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input pad_yy_icg_scan_en;
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input plic_core_me_int;
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input plic_core_se_int;
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output [1:0] core_pad_lpmd_b;
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output [2:0] sysio_core_hartid;
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output sysio_core_me_int;
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output sysio_core_ms_int;
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output sysio_core_mt_int;
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output sysio_core_se_int;
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output sysio_core_ss_int;
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output sysio_core_st_int;
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// &Regs; @24
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reg clint_core_ms_int_cpu;
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reg clint_core_mt_int_cpu;
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reg clint_core_ss_int_cpu;
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reg clint_core_st_int_cpu;
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reg [1:0] core_pad_lpmd_b;
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reg plic_core_me_int_cpu;
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reg plic_core_se_int_cpu;
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// &Wires; @25
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wire apb_clk_en;
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wire axim_clk_en;
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wire clint_core_ms_int;
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wire clint_core_mt_int;
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wire clint_core_ss_int;
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wire clint_core_st_int;
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wire [1:0] core_sysio_lpmd_b;
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wire cpurst_b;
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wire forever_cpuclk;
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wire kid_int_clk;
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wire kid_int_clk_en;
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wire pad_yy_icg_scan_en;
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wire plic_core_me_int;
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wire plic_core_se_int;
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wire sysio_clk_en;
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wire [2:0] sysio_core_hartid;
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wire sysio_core_me_int;
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wire sysio_core_ms_int;
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wire sysio_core_mt_int;
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wire sysio_core_se_int;
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wire sysio_core_ss_int;
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wire sysio_core_st_int;
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wire sysio_kid_clk;
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//input
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assign sysio_clk_en = axim_clk_en;
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// &Instance("gated_clk_cell", "x_sysio_kid_gated_clk"); @29
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gated_clk_cell x_sysio_kid_gated_clk (
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.clk_in (forever_cpuclk ),
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.clk_out (sysio_kid_clk ),
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.external_en (1'b0 ),
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.global_en (1'b1 ),
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.local_en (sysio_clk_en ),
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.module_en (1'b0 ),
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.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
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);
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// &Connect(.clk_in (forever_cpuclk), @30
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// .external_en (1'b0 ), @31
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// .global_en (1'b1 ), @32
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// .module_en (1'b0 ). @33
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// .local_en (sysio_clk_en ), @34
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// .clk_out (sysio_kid_clk ) @35
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// ); @36
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//output
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always @(posedge sysio_kid_clk or negedge cpurst_b)
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begin
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if (!cpurst_b)
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begin
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core_pad_lpmd_b[1:0] <= 2'b11;
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end
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else if (axim_clk_en)
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begin
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core_pad_lpmd_b[1:0] <= core_sysio_lpmd_b[1:0];
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end
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end
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// &Force("output", "sysio_core_me_int"); @51
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// &Force("output", "sysio_core_mt_int"); @52
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// &Force("output", "sysio_core_ms_int"); @53
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// &Force("output", "sysio_core_se_int"); @54
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// &Force("output", "sysio_core_st_int"); @55
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// &Force("output", "sysio_core_ss_int"); @56
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assign kid_int_clk_en = apb_clk_en;
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// &Instance("gated_clk_cell", "x_sysio_kid_int_gated_clk"); @59
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gated_clk_cell x_sysio_kid_int_gated_clk (
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.clk_in (forever_cpuclk ),
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.clk_out (kid_int_clk ),
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.external_en (1'b0 ),
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.global_en (1'b1 ),
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.local_en (kid_int_clk_en ),
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.module_en (1'b0 ),
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.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
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);
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// &Connect(.clk_in (forever_cpuclk), @60
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// .external_en (1'b0 ), @61
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// .global_en (1'b1 ), @62
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// .module_en (1'b0 ). @63
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// .local_en (kid_int_clk_en), @64
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// .clk_out (kid_int_clk ) @65
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// ); @66
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always @(posedge kid_int_clk or negedge cpurst_b)
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begin
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if (!cpurst_b)
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begin
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plic_core_me_int_cpu <= 1'b0;
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plic_core_se_int_cpu <= 1'b0;
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clint_core_ms_int_cpu <= 1'b0;
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clint_core_ss_int_cpu <= 1'b0;
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clint_core_mt_int_cpu <= 1'b0;
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clint_core_st_int_cpu <= 1'b0;
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end
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else if (apb_clk_en)
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begin
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plic_core_me_int_cpu <= plic_core_me_int;
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plic_core_se_int_cpu <= plic_core_se_int;
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clint_core_ms_int_cpu <= clint_core_ms_int;
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clint_core_ss_int_cpu <= clint_core_ss_int;
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clint_core_mt_int_cpu <= clint_core_mt_int;
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clint_core_st_int_cpu <= clint_core_st_int;
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end
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end
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assign sysio_core_me_int = plic_core_me_int_cpu;
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assign sysio_core_se_int = plic_core_se_int_cpu;
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assign sysio_core_ms_int = clint_core_ms_int_cpu;
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assign sysio_core_ss_int = clint_core_ss_int_cpu;
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assign sysio_core_mt_int = clint_core_mt_int_cpu;
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assign sysio_core_st_int = clint_core_st_int_cpu;
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// retroSoC: HP hart id is 1 (LP Hazard3 is hart 0); upstream ties this to 3'b0.
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assign sysio_core_hartid[2:0] = 3'd1;
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// &Force("output","core_pad_lpmd_b"); @100
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// &ModuleEnd; @103
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endmodule
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