mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
8d735aafbd
- Adjusted slot assignments in to reflect new peripheral mappings. - Updated to validate new OpenC906 configurations, including generator and profile checks. - Modified to reference the new Std-series VexiiRiscv generator. - Changed cache maintenance instructions in to align with C906 specifications. - Revised assertions in to account for internal unit removals. - Updated to reflect changes in peripheral interface counts and policies. - Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
73 lines
2.9 KiB
C
73 lines
2.9 KiB
C
// retroSoC controlled override of the vendored OpenC906 sysmap.h.
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//
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// Source: openc906 dependency (dependencies.lock.json "openc906"),
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// C906_RTL_FACTORY/gen_rtl/mmu/rtl/sysmap.h
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// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f
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// License: Apache-2.0 (T-Head Semiconductor)
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//
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// retroSoC change: the upstream default region table targets a 40-bit
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// reference map and marks the entire low 2.4 GiB (including the Mini
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// peripheral window) as cacheable/bufferable memory. The OpenC906 user
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// manual (section 3, sysmap.h) requires the integrator to configure address
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// attributes per SoC and explicitly requires CLINT/PLIC regions to be
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// non-cacheable devices. This override maps the Mini address map:
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//
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// region 0: 0x0000_0000-0x01FF_FFFF flash XIP -> normal cacheable
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// region 1: 0x0200_0000-0x2FFF_FFFF MMIO window (incl. the core-internal
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// CLINT/PLIC window 0x0800_0000-0x0FFF_FFFF) -> device SO/NC/NB
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// region 2: 0x3000_0000-0x4FFF_FFFF SRAM/SDRAM/PSRAM/OPI -> cacheable
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// region 3: 0x5000_0000-0x5FFF_FFFF XPI window -> normal cacheable
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// region 4: 0x6000_0000-0x7FFF_FFFF reserved -> device SO/NC/NB
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// region 5-7: everything above -> device SO/NC/NB (also the
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// out-of-table default per the user manual)
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//
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// Flag bit layout (aq_mmu_utlb.v: utlb_so=flg[9]=pma[4], utlb_ca=pma[3]):
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// flag[4]=SO (strong order) flag[3]=C (cacheable) flag[2]=B (bufferable)
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// flag[1]=shareable flag[0]=security (unused without TEE)
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//
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// Keep in sync when the lock revision changes.
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// ADDR is 28-bit, 4K address
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// Flag includes: Strong Order, Cacheable, Bufferable, Shareable, Security
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`define SYSMAP_BASE_ADDR0 28'h02000
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`define SYSMAP_FLG0 5'b01111
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`define SYSMAP_BASE_ADDR1 28'h30000
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`define SYSMAP_FLG1 5'b10011
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`define SYSMAP_BASE_ADDR2 28'h50000
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`define SYSMAP_FLG2 5'b01111
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`define SYSMAP_BASE_ADDR3 28'h60000
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`define SYSMAP_FLG3 5'b01111
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`define SYSMAP_BASE_ADDR4 28'h80000
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`define SYSMAP_FLG4 5'b10011
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`define SYSMAP_BASE_ADDR5 28'hC0000
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`define SYSMAP_FLG5 5'b10011
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`define SYSMAP_BASE_ADDR6 28'hFF00000
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`define SYSMAP_FLG6 5'b10011
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`define SYSMAP_BASE_ADDR7 28'hFFFFFFF
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`define SYSMAP_FLG7 5'b10011
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//End ct_mmu_sysmap
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