mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
8d735aafbd
- Adjusted slot assignments in to reflect new peripheral mappings. - Updated to validate new OpenC906 configurations, including generator and profile checks. - Modified to reference the new Std-series VexiiRiscv generator. - Changed cache maintenance instructions in to align with C906 specifications. - Revised assertions in to account for internal unit removals. - Updated to reflect changes in peripheral interface counts and policies. - Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
639 lines
22 KiB
Systemverilog
639 lines
22 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "mmap_define.svh"
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`include "soc_irq_config.svh"
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module apb4_periph #(
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parameter bit EnableP7 = 1'b0
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) (
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// verilog_format: off -- preserve reviewed column alignment
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input logic clk_i,
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input logic rst_n_i,
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input logic clk_aud_i,
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input logic rst_aud_n_i,
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input logic clk_ulpi_i,
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input logic clk_mem_i,
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input logic rst_mem_n_i,
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input logic clk_hp_i,
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input logic rst_hp_n_i,
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input logic debug_halted_i,
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input logic timebase_tick_i,
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input logic ext_h_hp_irq_i,
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input logic [8:0] resource_irq_lp_i,
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input logic [8:0] resource_irq_hp_i,
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input logic [1:0] apu_owner_i,
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input logic apu_owner_lock_i,
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input logic apu_quiesce_i,
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input logic apu_reset_i,
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input logic [7:0] apu_bridge_epoch_i,
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input logic jpeg_quiesce_i,
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input logic jpeg_reset_i,
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input logic ga2d_quiesce_i,
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input logic ga2d_reset_i,
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input logic ga2d_source_stop_i,
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input logic ga2d_source_safe_idle_i,
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input logic ga2d_block_ack_i,
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input logic ga2d_bridge_clear_busy_i,
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input logic [7:0] ga2d_bridge_epoch_i,
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input logic ga2d_data_ready_i,
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input logic [1:0] npu_owner_i,
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input logic npu_owner_lock_i,
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input logic npu_quiesce_i,
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input logic npu_reset_i,
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input logic npu_hp_block_new_i,
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input logic npu_hp_flush_i,
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input logic [1:0] mem_pad_mode_i,
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axi4_if.slave cfg_axi4,
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axi4_if.slave psram_axi4,
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axi4_if.slave xpi_axi4,
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axi4_if.master spisd_axi4,
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axi4_if.slave opipsram_axi4,
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gpio_if.dut gpio,
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user_gpio_if.padctrl user_gpio,
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uart_if.dut uart,
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uart_if.dut uart1,
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psram_if.dut psram,
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spi_if.dut spisd,
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i2c_if.dut i2c0,
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i2s_if.dut i2s,
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ws2812_if.dut ws2812,
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xpi_if.dut xpi,
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axi4_if.master dma_axi4,
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axi4_if.master sdio0_axi4,
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axi4_if.master sdio1_axi4,
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axi4_if.master usb2_axi4,
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axi4_if.master apu_axi4,
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axi4_if.master jpeg_axi4,
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axi4_if.master ga2d_axi4,
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axi4_if.master npu_axi4,
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sysctrl_if.dut sysctrl,
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pll_ctrl_if.sysctrl pll_ctrl,
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clock_ctrl_if.sysctrl clock_ctrl,
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apb4_if.master sdram_cfg,
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apb4_if.master sram_cfg,
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dvp_if.dut dvp,
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sdio_if.dut sdio0,
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sdio_if.dut sdio1,
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usb2_ulpi_if.dut usb2,
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opipsram_if.dut opipsram,
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i2c_if.dut i2c1,
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input logic fault_valid_i,
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input logic [31:0] fault_addr_i,
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input logic [3:0] fault_wstrb_i,
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input logic fault_reserved_i,
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output logic [63:0] hp_time_o,
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output logic [15:0] hp_plic_src_o,
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output logic apu_idle_o,
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output logic jpeg_idle_o,
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output logic ga2d_idle_o,
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output logic ga2d_core_safe_idle_o,
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output logic npu_idle_o,
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output logic npu_block_ack_o,
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output logic npu_hp_pause_ack_o,
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output logic npu_hp_flush_busy_o,
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output logic npu_hp_idle_o,
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output logic [8:0] resource_irq_raw_o,
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output logic [`SOC_IRQ_APB4_PERIPH_WIDTH-1:0] irq_o
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// verilog_format: on
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);
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// Generated timed and pure scalar APB interfaces preserve FPGA compatibility.
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`include "apb4_periph_interfaces.svh"
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`include "apb4_periph_bridges.svh"
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axi4_stream_if #(
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.DEST_WIDTH(1),
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.USER_WIDTH(1)
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) u_i2s_tx_axis_if (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.DEST_WIDTH(1),
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.USER_WIDTH(1)
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) u_i2s_rx_axis_if (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.DEST_WIDTH(1),
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.USER_WIDTH(1)
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) u_dma_i2s_tx_axis_if (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.DEST_WIDTH(1),
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.USER_WIDTH(1)
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) u_dma_i2s_rx_axis_if (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.DEST_WIDTH(1),
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.USER_WIDTH(1)
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) u_dvp_rx_axis_if (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.DEST_WIDTH(1),
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.USER_WIDTH(1)
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) u_crypto_in_axis_if (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.DEST_WIDTH(1),
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.USER_WIDTH(1)
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) u_crypto_out_axis_if (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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clint_if u_clint_if ();
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dma_req_if u_dma_req_if ();
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apb4_if u_psram_mem_apb4_if (
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.pclk (clk_mem_i),
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.presetn(rst_mem_n_i)
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);
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apb4_if u_xpi_mem_apb4_if (
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.pclk (clk_mem_i),
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.presetn(rst_mem_n_i)
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);
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apb4_if u_opipsram_mem_apb4_if (
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.pclk (clk_mem_i),
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.presetn(rst_mem_n_i)
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);
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psram_if u_psram_mem_if ();
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opipsram_if u_opipsram_mem_if ();
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logic s_dma_i2s_tx_stall, s_dma_i2s_rx_stall;
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logic s_dma_xpi_tx_stall, s_dma_xpi_rx_stall;
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logic s_dma_uart_tx_stall, s_dma_uart_rx_stall;
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logic s_dma_i2c0_tx_stall, s_dma_i2c0_rx_stall;
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logic s_dma_i2c1_tx_stall, s_dma_i2c1_rx_stall;
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logic s_dma_xfer_done;
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logic s_dma_irq;
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logic s_dma_crypto_in_proc;
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logic s_dma_crypto_out_proc;
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logic s_crypto_irq;
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logic s_apu_irq_raw;
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logic s_i2s_tx_underrun_evt, s_i2s_rx_overrun_evt;
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logic s_i2s_rx_flush_busy;
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logic s_jpeg_irq_raw;
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logic s_ga2d_irq_raw;
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logic s_npu_irq_raw;
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logic s_usb2_irq;
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logic s_tim0_irq, s_tim1_irq;
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logic s_dvp_irq;
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logic s_xpi_irq;
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logic s_xpi_irq_mem;
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logic s_psram_irq_mem;
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logic s_opipsram_irq_mem;
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logic s_dma_xfer_done_mem;
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logic s_dma_xpi_tx_stall_mem;
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logic s_dma_xpi_rx_stall_mem;
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logic s_mailbox_lp_irq, s_mailbox_hp_irq;
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logic [15:0] s_hp_plic_source;
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logic [ 3:0] s_unused_optional_status;
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axi42apb4_periph u_axi42apb4_periph (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.axi4 (cfg_axi4),
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`include "apb4_periph_connections.svh"
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);
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assign u_dma_req_if.i2s_tx_proc = ~s_dma_i2s_tx_stall;
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assign u_dma_req_if.i2s_rx_proc = ~s_dma_i2s_rx_stall;
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assign u_dma_req_if.qspi_tx_proc = ~s_dma_xpi_tx_stall;
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assign u_dma_req_if.qspi_rx_proc = ~s_dma_xpi_rx_stall;
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assign u_dma_req_if.uart_tx_proc = ~s_dma_uart_tx_stall;
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assign u_dma_req_if.uart_rx_proc = ~s_dma_uart_rx_stall;
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assign u_dma_req_if.i2c0_tx_proc = ~s_dma_i2c0_tx_stall;
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assign u_dma_req_if.i2c0_rx_proc = ~s_dma_i2c0_rx_stall;
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assign u_dma_req_if.i2c1_tx_proc = ~s_dma_i2c1_tx_stall;
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assign u_dma_req_if.i2c1_rx_proc = ~s_dma_i2c1_rx_stall;
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assign u_dma_req_if.crypto_in_proc = s_dma_crypto_in_proc;
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assign u_dma_req_if.crypto_out_proc = s_dma_crypto_out_proc;
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assign hp_time_o = u_clint_if.mtime_o;
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assign hp_plic_src_o = s_hp_plic_source;
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assign resource_irq_raw_o = {
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s_npu_irq_raw,
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s_ga2d_irq_raw,
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s_apu_irq_raw,
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s_jpeg_irq_raw,
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spisd.irq_o,
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sdio1.irq_o,
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sdio0.irq_o,
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s_usb2_irq,
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s_dma_irq
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};
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apb4_async_bridge u_psram_cfg_mem_cdc (
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.src_clk_i (clk_i),
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.src_rst_n_i(rst_n_i),
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.dst_clk_i (clk_mem_i),
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.dst_rst_n_i(rst_mem_n_i),
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.src_apb4 (u_psram_apb4_if),
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.dst_apb4 (u_psram_mem_apb4_if)
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);
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apb4_async_bridge u_xpi_cfg_mem_cdc (
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.src_clk_i (clk_i),
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.src_rst_n_i(rst_n_i),
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.dst_clk_i (clk_mem_i),
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.dst_rst_n_i(rst_mem_n_i),
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.src_apb4 (u_xpi_apb4_if),
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.dst_apb4 (u_xpi_mem_apb4_if)
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);
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apb4_async_bridge u_opipsram_cfg_mem_cdc (
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.src_clk_i (clk_i),
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.src_rst_n_i(rst_n_i),
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.dst_clk_i (clk_mem_i),
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.dst_rst_n_i(rst_mem_n_i),
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.src_apb4 (u_opipsram_apb4_if),
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.dst_apb4 (u_opipsram_mem_apb4_if)
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);
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cdc_event_bridge u_xpi_dma_done_cdc (
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.src_clk_i (clk_i),
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.src_rst_n_i (rst_n_i),
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.event_i (s_dma_xfer_done),
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.source_ready_o(s_unused_optional_status[0]),
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.source_busy_o (s_unused_optional_status[1]),
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.dst_clk_i (clk_mem_i),
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.dst_rst_n_i (rst_mem_n_i),
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.event_o (s_dma_xfer_done_mem)
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);
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cdc_sync #(
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.STAGE (2),
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.DATA_WIDTH(5)
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) u_memory_status_sync (
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.clk_i(clk_i),
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.rst_n_i(rst_n_i),
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.dat_i({
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s_xpi_irq_mem,
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s_psram_irq_mem,
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s_opipsram_irq_mem,
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s_dma_xpi_tx_stall_mem,
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s_dma_xpi_rx_stall_mem
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}),
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.dat_o({s_xpi_irq, psram.irq_o, opipsram.irq_o, s_dma_xpi_tx_stall, s_dma_xpi_rx_stall})
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);
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assign psram.sck_o = u_psram_mem_if.sck_o;
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assign psram.nss_o = u_psram_mem_if.nss_o;
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assign psram.io_oe_o = u_psram_mem_if.io_oe_o;
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assign psram.io_do_o = u_psram_mem_if.io_do_o;
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assign u_psram_mem_if.io_di_i = psram.io_di_i;
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assign s_psram_irq_mem = u_psram_mem_if.irq_o;
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assign opipsram.ck_o = u_opipsram_mem_if.ck_o;
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assign opipsram.cs_n_o = u_opipsram_mem_if.cs_n_o;
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assign opipsram.dq_oe_o = u_opipsram_mem_if.dq_oe_o;
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assign opipsram.dq_o = u_opipsram_mem_if.dq_o;
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assign opipsram.rwds_oe_o = u_opipsram_mem_if.rwds_oe_o;
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assign opipsram.rwds_o = u_opipsram_mem_if.rwds_o;
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assign u_opipsram_mem_if.dq_i = opipsram.dq_i;
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assign u_opipsram_mem_if.rwds_i = opipsram.rwds_i;
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assign s_opipsram_irq_mem = u_opipsram_mem_if.irq_o;
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always_comb begin
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s_hp_plic_source = '0;
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s_hp_plic_source[1] = uart1.irq_o;
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s_hp_plic_source[2] = s_mailbox_hp_irq;
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s_hp_plic_source[3] = ext_h_hp_irq_i;
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s_hp_plic_source[4] = resource_irq_hp_i[0];
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s_hp_plic_source[5] = resource_irq_hp_i[1];
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s_hp_plic_source[6] = resource_irq_hp_i[2];
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s_hp_plic_source[7] = resource_irq_hp_i[3];
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s_hp_plic_source[8] = resource_irq_hp_i[4];
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s_hp_plic_source[9] = resource_irq_hp_i[5];
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s_hp_plic_source[10] = resource_irq_hp_i[6];
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s_hp_plic_source[11] = resource_irq_hp_i[7];
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s_hp_plic_source[12] = resource_irq_hp_i[8];
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end
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`include "apb4_periph_irq_bindings.svh"
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// verilog_format: off -- preserve reviewed column alignment
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apb4_gpio #(
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.UserBaseAddr (`SOC_ADDR_APB4_GPIO_BASE),
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.AdminBaseAddr(`SOC_ADDR_APB4_GPIO_ADMIN_BASE),
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.HasInputCmos (gpio_pad_caps_pkg::HasInputCmos),
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.HasPullUp (gpio_pad_caps_pkg::HasPullUp),
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.HasPullDown (gpio_pad_caps_pkg::HasPullDown)
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) u_apb4_gpio (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.apb4 (u_gpio_apb4_if),
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.gpio (gpio),
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.user_gpio (user_gpio)
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);
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// verilog_format: on
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apb4_uart u_apb4_uart (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_tx_stall_o(s_dma_uart_tx_stall),
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.dma_rx_stall_o(s_dma_uart_rx_stall),
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.apb4 (u_uart_apb4_if),
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.uart (uart)
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);
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// UART1 is dedicated to HP Linux and intentionally has no central-DMA route in the MVP.
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apb4_uart u_apb4_uart1 (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_tx_stall_o(s_unused_optional_status[2]),
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.dma_rx_stall_o(s_unused_optional_status[3]),
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.apb4 (u_uart1_apb4_if),
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.uart (uart1)
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);
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apb4_hp_mailbox u_apb4_hp_mailbox (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.apb4 (u_hp_mailbox_apb4_if),
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.lp_irq_o(s_mailbox_lp_irq),
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.hp_irq_o(s_mailbox_hp_irq)
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);
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apb4_timer u_apb4_timer0 (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.debug_halted_i(debug_halted_i),
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.apb4 (u_tim0_apb4_if),
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.irq_o (s_tim0_irq)
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);
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apb4_timer u_apb4_timer1 (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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|
.debug_halted_i(debug_halted_i),
|
|
.apb4 (u_tim1_apb4_if),
|
|
.irq_o (s_tim1_irq)
|
|
);
|
|
|
|
apb4_psram u_apb4_psram (
|
|
.clk_i (clk_mem_i),
|
|
.rst_n_i (rst_mem_n_i),
|
|
.cfg_apb4(u_psram_mem_apb4_if),
|
|
.mem_axi4(psram_axi4),
|
|
.psram (u_psram_mem_if)
|
|
);
|
|
|
|
apb4_spisd u_apb4_spisd (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.apb4 (u_spisd_apb4_if),
|
|
.dma_axi4(spisd_axi4),
|
|
.spi (spisd)
|
|
);
|
|
|
|
apb4_i2c u_apb4_i2c0 (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.dma_tx_stall_o(s_dma_i2c0_tx_stall),
|
|
.dma_rx_stall_o(s_dma_i2c0_rx_stall),
|
|
.apb4 (u_i2c0_apb4_if),
|
|
.i2c (i2c0)
|
|
);
|
|
|
|
apb4_i2s u_apb4_i2s (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.clk_aud_i (clk_aud_i),
|
|
.rst_aud_n_i (rst_aud_n_i),
|
|
.dma_tx_stall_o (s_dma_i2s_tx_stall),
|
|
.dma_rx_stall_o (s_dma_i2s_rx_stall),
|
|
.tx_underrun_evt_o(s_i2s_tx_underrun_evt),
|
|
.rx_overrun_evt_o (s_i2s_rx_overrun_evt),
|
|
.rx_flush_busy_o (s_i2s_rx_flush_busy),
|
|
.apb4 (u_i2s_apb4_if),
|
|
.tx_axis (u_i2s_tx_axis_if),
|
|
.rx_axis (u_i2s_rx_axis_if),
|
|
.i2s (i2s)
|
|
);
|
|
|
|
apb4_ws2812 u_apb4_ws2812 (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.apb4 (u_ws2812_apb4_if),
|
|
.ws2812 (ws2812)
|
|
);
|
|
|
|
apb4_xpi u_apb4_xpi (
|
|
.clk_i (clk_mem_i),
|
|
.rst_n_i (rst_mem_n_i),
|
|
.dma_xfer_done_i(s_dma_xfer_done_mem),
|
|
.dma_tx_stall_o (s_dma_xpi_tx_stall_mem),
|
|
.dma_rx_stall_o (s_dma_xpi_rx_stall_mem),
|
|
.irq_o (s_xpi_irq_mem),
|
|
.apb4 (u_xpi_mem_apb4_if),
|
|
.mem_axi4 (xpi_axi4),
|
|
.xpi (xpi)
|
|
);
|
|
|
|
apb4_dma #(
|
|
.NumChannels(8),
|
|
.FifoDepth (32)
|
|
) u_apb4_dma (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.dma_xfer_done_o(s_dma_xfer_done),
|
|
.irq_o (s_dma_irq),
|
|
.hw_trg (u_dma_req_if),
|
|
.apb4 (u_dma_apb4_if),
|
|
.axi4 (dma_axi4),
|
|
.i2s_tx_axis (u_dma_i2s_tx_axis_if),
|
|
.i2s_rx_axis (u_dma_i2s_rx_axis_if),
|
|
.dvp_rx_axis (u_dvp_rx_axis_if),
|
|
.crypto_in_axis (u_crypto_in_axis_if),
|
|
.crypto_out_axis(u_crypto_out_axis_if)
|
|
);
|
|
|
|
apb4_crypto u_apb4_crypto (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.dma_input_proc_o (s_dma_crypto_in_proc),
|
|
.dma_output_proc_o(s_dma_crypto_out_proc),
|
|
.irq_o (s_crypto_irq),
|
|
.apb4 (u_crypto_apb4_if),
|
|
.crypto_in_axis (u_crypto_in_axis_if),
|
|
.crypto_out_axis (u_crypto_out_axis_if)
|
|
);
|
|
|
|
apb4_jpeg u_apb4_jpeg (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.quiesce_i (jpeg_quiesce_i),
|
|
.resource_reset_i(jpeg_reset_i),
|
|
.apb4 (u_jpeg_apb4_if),
|
|
.axi4 (jpeg_axi4),
|
|
.idle_o (jpeg_idle_o),
|
|
.irq_o (s_jpeg_irq_raw)
|
|
);
|
|
|
|
apb4_apu #(
|
|
.EnableP7(EnableP7)
|
|
) u_apb4_apu (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.owner_i (apu_owner_i),
|
|
.owner_lock_i (apu_owner_lock_i),
|
|
.quiesce_i (apu_quiesce_i),
|
|
.resource_reset_i (apu_reset_i),
|
|
.bridge_epoch_i (apu_bridge_epoch_i),
|
|
.i2s_tx_underrun_i (s_i2s_tx_underrun_evt),
|
|
.i2s_rx_overrun_i (s_i2s_rx_overrun_evt),
|
|
.i2s_rx_flush_busy_i(s_i2s_rx_flush_busy),
|
|
.apb4 (u_apu_apb4_if),
|
|
.axi4 (apu_axi4),
|
|
.dma_tx_axis (u_dma_i2s_tx_axis_if),
|
|
.dma_rx_axis (u_dma_i2s_rx_axis_if),
|
|
.i2s_tx_axis (u_i2s_tx_axis_if),
|
|
.i2s_rx_axis (u_i2s_rx_axis_if),
|
|
.idle_o (apu_idle_o),
|
|
.irq_o (s_apu_irq_raw)
|
|
);
|
|
|
|
apb4_ga2d u_apb4_ga2d (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.resource_quiesce_i (ga2d_quiesce_i),
|
|
.resource_reset_i (ga2d_reset_i),
|
|
.source_stop_i (ga2d_source_stop_i),
|
|
.source_safe_idle_i (ga2d_source_safe_idle_i),
|
|
.block_ack_i (ga2d_block_ack_i),
|
|
.bridge_clear_busy_i(ga2d_bridge_clear_busy_i),
|
|
.bridge_epoch_i (ga2d_bridge_epoch_i),
|
|
.data_ready_i (ga2d_data_ready_i),
|
|
.mem_pad_mode_i (mem_pad_mode_i),
|
|
.apb4 (u_ga2d_apb4_if),
|
|
.ga2d_axi4 (ga2d_axi4),
|
|
.idle_o (ga2d_idle_o),
|
|
.core_safe_idle_o (ga2d_core_safe_idle_o),
|
|
.irq_o (s_ga2d_irq_raw)
|
|
);
|
|
|
|
apb4_npu u_apb4_npu (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.clk_hp_i (clk_hp_i),
|
|
.rst_hp_n_i (rst_hp_n_i),
|
|
.resource_owner_i (npu_owner_i),
|
|
.resource_owner_lock_i(npu_owner_lock_i),
|
|
.resource_quiesce_i (npu_quiesce_i),
|
|
.resource_reset_i (npu_reset_i),
|
|
.apb4 (u_npu_apb4_if),
|
|
.idle_o (npu_idle_o),
|
|
.block_ack_o (npu_block_ack_o),
|
|
.irq_o (s_npu_irq_raw),
|
|
.hp_block_new_i (npu_hp_block_new_i),
|
|
.hp_pause_ack_o (npu_hp_pause_ack_o),
|
|
.hp_flush_i (npu_hp_flush_i),
|
|
.hp_flush_busy_o (npu_hp_flush_busy_o),
|
|
.hp_idle_o (npu_hp_idle_o),
|
|
.npu_axi4 (npu_axi4)
|
|
);
|
|
|
|
apb4_sysctrl u_apb4_sysctrl (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.fault_valid_i (fault_valid_i),
|
|
.fault_addr_i (fault_addr_i),
|
|
.fault_wstrb_i (fault_wstrb_i),
|
|
.fault_reserved_i(fault_reserved_i),
|
|
.apb4 (u_sysctrl_apb4_if),
|
|
.sysctrl (sysctrl),
|
|
.pll_ctrl (pll_ctrl),
|
|
.clock_ctrl (clock_ctrl)
|
|
);
|
|
|
|
apb4_clint u_apb4_clint (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.timebase_tick_i(timebase_tick_i),
|
|
.apb4 (u_clint_apb4_if),
|
|
.clint (u_clint_if)
|
|
);
|
|
|
|
axi4s_dvp u_axi4_dvp (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.apb4 (u_dvp_apb4_if),
|
|
.rx_axis(u_dvp_rx_axis_if),
|
|
.dvp (dvp),
|
|
.irq_o (s_dvp_irq)
|
|
);
|
|
|
|
apb4_sdio u_apb4_sdio0 (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.apb4 (u_sdio0_apb4_if),
|
|
.dma_axi4(sdio0_axi4),
|
|
.sdio (sdio0)
|
|
);
|
|
|
|
apb4_sdio u_apb4_sdio1 (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.apb4 (u_sdio1_apb4_if),
|
|
.dma_axi4(sdio1_axi4),
|
|
.sdio (sdio1)
|
|
);
|
|
|
|
apb4_usb2 u_apb4_usb2 (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.clk_ulpi_i(clk_ulpi_i),
|
|
.apb4 (u_usb2_apb4_if),
|
|
.dma_axi4 (usb2_axi4),
|
|
.irq_o (s_usb2_irq),
|
|
.ulpi (usb2)
|
|
);
|
|
|
|
apb4_opipsram u_apb4_opipsram (
|
|
.clk_i (clk_mem_i),
|
|
.rst_n_i (rst_mem_n_i),
|
|
.clk_phy_i (clk_mem_i),
|
|
.rst_phy_n_i(rst_mem_n_i),
|
|
.cfg_apb4 (u_opipsram_mem_apb4_if),
|
|
.mem_axi4 (opipsram_axi4),
|
|
.psram (u_opipsram_mem_if)
|
|
);
|
|
|
|
apb4_i2c u_apb4_i2c1 (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.dma_tx_stall_o(s_dma_i2c1_tx_stall),
|
|
.dma_rx_stall_o(s_dma_i2c1_rx_stall),
|
|
.apb4 (u_i2c1_apb4_if),
|
|
.i2c (i2c1)
|
|
);
|
|
|
|
endmodule
|