mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
8d735aafbd
- Adjusted slot assignments in to reflect new peripheral mappings. - Updated to validate new OpenC906 configurations, including generator and profile checks. - Modified to reference the new Std-series VexiiRiscv generator. - Changed cache maintenance instructions in to align with C906 specifications. - Revised assertions in to account for internal unit removals. - Updated to reflect changes in peripheral interface counts and policies. - Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
128 lines
3.6 KiB
Scala
128 lines
3.6 KiB
Scala
package vexiiriscv
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import spinal.core._
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import spinal.lib.bus.misc.SizeMapping
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import spinal.lib.bus.tilelink.M2sTransfers
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import spinal.lib.system.tag.PmaRegionImpl
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import vexiiriscv.misc.EmbeddedRiscvJtag
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import java.nio.file.{Files, Paths}
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/** Generates the fixed retroSoC Std-series RV64 application core configuration
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* (preserved from the retired Mini HP configuration).
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*/
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object GenerateRetroSocStd extends App {
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require(args.length == 1, "usage: GenerateRetroSocStd <output-directory>")
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val output = Paths.get(args(0)).toAbsolutePath.normalize
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Files.createDirectories(output)
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val param = new ParamSimple()
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param.xlen = 64
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param.physicalWidth = 32
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param.resetVector = 0x38000000L
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param.asidWidth = 9
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param.addISA("m", "a", "f", "d", "c", "s", "u", "zicbom", "zicntr", "zihpm")
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param.fixIsaParams()
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param.decoders = 2
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param.lanes = 2
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param.withBtb = true
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param.withGShare = true
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param.withRas = true
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param.withLateAlu = true
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param.withAlignerBuffer = true
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param.withDispatcherBuffer = true
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param.allowBypassFrom = 0
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param.storeRs2Late = true
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param.divRadix = 4
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param.divArea = false
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param.fetchL1Enable = true
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param.fetchL1Sets = 64
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param.fetchL1Ways = 4
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param.fetchMemDataWidthMin = 64
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param.fetchL1RefillCount = 2
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param.fetchL1Prefetch = "nl"
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param.fetchBus = FetchBusEnum.axi4
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param.lsuL1Enable = true
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param.lsuL1Sets = 64
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param.lsuL1Ways = 4
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param.lsuMemDataWidthMin = 64
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param.lsuL1RefillCount = 8
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param.lsuL1WritebackCount = 8
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param.lsuStoreBufferSlots = 4
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param.lsuStoreBufferOps = 32
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param.lsuSoftwarePrefetch = true
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param.lsuHardwarePrefetch = "rpt"
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param.withLsuBypass = true
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param.lsuBus = LsuBusEnum.axi4
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param.lsuL1Bus = LsuL1BusEnum.axi4
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param.pmpParam.pmpSize = 16
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param.pmpParam.granularity = 4096
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param.additionalPerformanceCounters = 8
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param.privParam.withRdTime = true
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param.privParam.withDebug = true
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param.privParam.debugTriggers = 4
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param.embeddedJtagTap = true
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val config = SpinalConfig(
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targetDirectory = output.toString,
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inlineRom = true
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)
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config.generateVerilog {
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val plugins = param.plugins(hartId = 1)
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plugins.foreach {
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case plugin: EmbeddedRiscvJtag =>
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plugin.debugCd = ClockDomain.current.copy(
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reset = Bool().setName("EmbeddedRiscvJtag_logic_debug_reset")
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)
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case _ =>
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}
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ParamSimple.setPma(
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plugins,
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Seq(
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new PmaRegionImpl(
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mapping = SizeMapping(0x00000000L, 0x01000000L),
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isMain = false,
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isExecutable = true,
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transfers = M2sTransfers.all
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),
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new PmaRegionImpl(
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mapping = SizeMapping(0x02000000L, 0x2E000000L),
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isMain = false,
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isExecutable = false,
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transfers = M2sTransfers.all
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),
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new PmaRegionImpl(
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mapping = SizeMapping(0x30000000L, 0x00020000L),
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isMain = true,
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isExecutable = true,
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transfers = M2sTransfers.all
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),
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new PmaRegionImpl(
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mapping = SizeMapping(0x38000000L, 0x04000000L),
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isMain = true,
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isExecutable = true,
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transfers = M2sTransfers.all
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),
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new PmaRegionImpl(
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mapping = SizeMapping(0x40000000L, 0x02000000L),
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isMain = true,
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isExecutable = true,
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transfers = M2sTransfers.all
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),
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new PmaRegionImpl(
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mapping = SizeMapping(0x48000000L, 0x08000000L),
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isMain = true,
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isExecutable = true,
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transfers = M2sTransfers.all
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)
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)
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)
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VexiiRiscv(plugins).setDefinitionName("vexiiriscv_std_generated")
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}
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}
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