mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
8f5630fb41
Connect DVP to Tiny DMA2/request 11, IRQ15 and the camera pad/reset lifecycle. Harden shared capture CDC, frame statistics, per-row size validation and HAL cleanup while preserving the Mini DMA3 binding and existing register ABI. Add deterministic capture/recovery firmware, source-bound evidence tooling, focused RTL/host tests and compact netlist acceptance. Preserve SAFE24, 128 KiB main SRAM, private Crypto storage and the locked dependencies. Retained validation: focused RTL, host/policy checks, Mini firmware, and ICS55/IHP130 RECOVERY, QVGA, synthesis and boot/DVP netlist checks pass. Full-system VGA remains historical; long full Icarus and broad regressions remain deferred. Global publication/format gaps and negative observational STA are retained, not reported as passing qualification. Specification: docs/ip/tiny-soc.md, TINY-R2-P9. Evidence: docs/ip/tiny-soc-verification.md.
66 lines
2.7 KiB
Systemverilog
66 lines
2.7 KiB
Systemverilog
// P7-only assertions over production paths. No DUT state is written.
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logic s_p7_monitor = 0;
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longint unsigned s_p7_gated_cycles = 0, s_p7_dma_gated_responses = 0;
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integer s_p7_warm_resets = 0;
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logic [3:0] s_p7_profiles = 0;
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initial s_p7_monitor = $test$plusargs("p7_monitor");
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initial begin
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if ($test$plusargs("p7_monitor") || $test$plusargs("p7_cold_reset_probe")) begin
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wait (s_rst_n === 1'b0);
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@(posedge s_rst_n);
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wait (u_dut.u_soc.s_cpu_boot_ready === 1'b1);
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repeat (2) @(negedge u_dut.u_soc.s_ref_clk);
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// Case comparisons require the exact known reset values in both simulators.
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if (u_dut.u_soc.u_sysctrl.s_reset_cause_q !== 32'd1 ||
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u_dut.u_soc.u_sysctrl.s_rcu_fault_q !== 32'd0 ||
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u_dut.u_soc.s_backend_current !== 2'd0 || u_dut.u_soc.s_gate_request !== 15'd0)
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$fatal(
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1,
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"SIM_TEST_FAIL P7 cold reset state cause=%h fault=%h profile=%h gates=%h",
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u_dut.u_soc.u_sysctrl.s_reset_cause_q,
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u_dut.u_soc.u_sysctrl.s_rcu_fault_q,
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u_dut.u_soc.s_backend_current,
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u_dut.u_soc.s_gate_request
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);
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if ($test$plusargs("p7_cold_reset_probe")) begin
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$display("P7_COLD_RESET_PASS");
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$finish; // Diagnostic only; never emits the full Tiny acceptance marker.
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end
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end
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end
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always @(posedge u_dut.u_soc.s_exec_clk) begin
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if (s_p7_monitor && u_dut.u_soc.s_actual_gate[0]) begin
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s_p7_gated_cycles++;
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if (u_dut.u_soc.u_masters_axi4_if[1].bvalid && u_dut.u_soc.u_masters_axi4_if[1].bready)
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s_p7_dma_gated_responses++;
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end
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end
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always @(posedge u_dut.u_soc.s_ref_clk) begin
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if (s_p7_monitor && u_dut.u_soc.s_clock_done) begin
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s_p7_profiles[u_dut.u_soc.s_backend_current] = 1;
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$display("P7_CLOCK_COMMIT profile=%0d sys=%0d mem=%0d pclk=%0d", u_dut.u_soc.s_backend_current,
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u_dut.u_soc.s_backend_sys_hz, u_dut.u_soc.s_backend_mem_hz,
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u_dut.u_soc.s_backend_pclk_hz);
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$fflush();
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end
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if (s_p7_monitor && u_dut.u_soc.s_system_reset) begin
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s_p7_warm_resets++;
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$display("P7_SOFTWARE_RESET request=%0d", s_p7_warm_resets);
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$fflush();
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end
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end
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final begin
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if (s_p7_monitor && u_dut.s_test_done && u_dut.s_test_pass) begin
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if (s_p7_gated_cycles == 0 || s_p7_dma_gated_responses == 0 || s_p7_warm_resets != 1)
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$fatal(1, "SIM_TEST_FAIL P7 WFI/DMA/software-reset coverage");
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`ifdef HAVE_PLL
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if ((s_p7_profiles & 4'b1101) != 4'b1101) $fatal(1, "SIM_TEST_FAIL P7 PLL profile coverage");
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`else
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if ((s_p7_profiles & 4'b0011) != 4'b0011)
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$fatal(1, "SIM_TEST_FAIL P7 external profile coverage");
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`endif
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$display("P7_LIFECYCLE_PASS gated_cycles=%0d dma_responses_while_gated=%0d warm_resets=%0d",
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s_p7_gated_cycles, s_p7_dma_gated_responses, s_p7_warm_resets);
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end
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end
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