mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-05 06:32:37 +00:00
maksyuki
8f5630fb41
Connect DVP to Tiny DMA2/request 11, IRQ15 and the camera pad/reset lifecycle. Harden shared capture CDC, frame statistics, per-row size validation and HAL cleanup while preserving the Mini DMA3 binding and existing register ABI. Add deterministic capture/recovery firmware, source-bound evidence tooling, focused RTL/host tests and compact netlist acceptance. Preserve SAFE24, 128 KiB main SRAM, private Crypto storage and the locked dependencies. Retained validation: focused RTL, host/policy checks, Mini firmware, and ICS55/IHP130 RECOVERY, QVGA, synthesis and boot/DVP netlist checks pass. Full-system VGA remains historical; long full Icarus and broad regressions remain deferred. Global publication/format gaps and negative observational STA are retained, not reported as passing qualification. Specification: docs/ip/tiny-soc.md, TINY-R2-P9. Evidence: docs/ip/tiny-soc-verification.md.
751 lines
13 KiB
JSON
751 lines
13 KiB
JSON
{
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"schema_version": 1,
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"cpu": {
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"module": "hazard3_cpu_2port",
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"local_ports": 2,
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"data_outstanding": 1
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},
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"main_sram": {
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"groups": 4,
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"group_bytes": 32768,
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"macros_per_group": 8,
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"macro_bytes": 4096,
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"base": "0x30000000",
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"macro_instance": "u_soc.u_sram.gen_group[{group}].u_group.gen_bank[{bank}].u_ram.u_mem",
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"external_attachment": "per-target-P5"
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},
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"fabric": {
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"owners": [
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"cpu_slow",
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"central_dma",
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"sdio"
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],
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"active_owners": [
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0,
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1,
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2
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],
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"cpu_combined_outstanding": 1,
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"dma_direction_outstanding": 1,
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"sdio_direction_outstanding": 1,
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"target_combined_outstanding": 1,
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"sram_targets": [
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0,
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1,
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2,
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3
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],
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"xpi_target": 4,
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"apb_target_base": 5,
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"decode_error_target": 26,
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"protocol_error_target": 27,
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"target_count": 28
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},
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"gpio_pins": 32,
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"irq_vector_width": 32,
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"external_irq_count": 30,
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"dma_channels": 8,
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"apb_targets": [
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{
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"name": "gpio",
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"regions": [
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"APB4_GPIO",
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"APB4_GPIO_ADMIN"
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]
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},
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{
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"name": "uart0",
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"regions": [
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"APB4_UART0"
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]
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},
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{
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"name": "timer0",
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"regions": [
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"APB4_TIM0"
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]
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},
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{
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"name": "timer1",
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"regions": [
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"APB4_TIM1"
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]
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},
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{
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"name": "i2c0",
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"regions": [
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"APB4_I2C0"
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]
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},
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{
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"name": "xpi",
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"regions": [
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"APB4_XPI"
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]
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},
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{
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"name": "dma",
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"regions": [
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"APB4_DMA"
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]
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},
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{
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"name": "sysctrl",
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"regions": [
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"APB4_SYSCTRL"
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]
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},
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{
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"name": "clint",
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"regions": [
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"APB4_CLINT"
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]
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},
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{
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"name": "sram",
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"regions": [
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"APB4_SRAM"
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]
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},
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{
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"name": "archinfo",
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"regions": [
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"APB4_ARCHINFO"
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]
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},
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{
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"name": "pwm",
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"regions": [
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"APB4_PWM"
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]
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},
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{
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"name": "rtc",
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"regions": [
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"APB4_RTC"
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]
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},
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{
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"name": "wdg",
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"regions": [
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"APB4_WDG"
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]
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},
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{
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"name": "rng",
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"regions": [
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"APB4_RNG"
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]
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},
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{
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"name": "crc",
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"regions": [
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"APB4_CRC"
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]
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},
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{
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"name": "ws2812",
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"regions": [
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"APB4_WS2812"
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]
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},
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{
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"name": "crypto",
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"regions": [
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"APB4_CRYPTO"
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]
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},
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{
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"name": "i2s",
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"regions": [
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"APB4_I2S"
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]
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},
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{
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"name": "sdio",
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"regions": [
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"APB4_SDIO0"
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]
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},
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{
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"name": "dvp",
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"regions": [
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"APB4_DVP"
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]
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}
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],
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"interrupts": [
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{
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"name": "clint_software",
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"core_bit": 0,
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"signal": "u_clint_if.software_irq_o[0]"
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},
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{
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"name": "clint_timer",
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"core_bit": 1,
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"signal": "u_clint_if.timer_irq_o[0]"
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},
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{
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"name": "uart0",
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"core_bit": 2,
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"signal": "u_uart0_if.irq_o"
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},
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{
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"name": "timer0",
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"core_bit": 3,
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"signal": "s_timer0_irq"
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},
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{
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"name": "timer1",
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"core_bit": 4,
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"signal": "s_timer1_irq"
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},
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{
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"name": "i2c0",
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"core_bit": 7,
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"signal": "u_i2c0_if.irq_o"
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},
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{
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"name": "i2s",
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"core_bit": 8,
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"signal": "u_i2s_if.irq_o"
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},
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{
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"name": "xpi",
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"core_bit": 9,
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"signal": "s_xpi_irq"
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},
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{
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"name": "sdio",
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"core_bit": 10,
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"signal": "u_sdio_if.irq_o"
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},
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{
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"name": "dvp",
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"core_bit": 15,
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"signal": "s_dvp_irq"
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},
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{
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"name": "pwm",
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"core_bit": 11,
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"signal": "u_pwm_if.irq_o"
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},
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{
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"name": "rtc",
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"core_bit": 13,
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"signal": "u_rtc_if.irq_o"
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},
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{
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"name": "watchdog_early_warning",
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"core_bit": 14,
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"signal": "u_wdg_if.irq_o"
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},
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{
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"name": "rng",
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"core_bit": 16,
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"signal": "s_rng_irq"
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},
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{
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"name": "ws2812",
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"core_bit": 17,
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"signal": "u_ws2812_if.irq_o"
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},
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{
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"name": "gpio",
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"core_bit": 18,
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"signal": "u_gpio_if.irq_o"
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},
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{
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"name": "dma",
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"core_bit": 20,
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"signal": "s_dma_irq"
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},
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{
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"name": "crypto",
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"core_bit": 23,
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"signal": "s_crypto_irq"
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},
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{
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"name": "rcu",
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"core_bit": 31,
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"signal": "s_rcu_irq"
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}
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],
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"gpio_alt_functions": [
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{
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"pin": 0,
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"alt0": {
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"inputs": [],
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"do": "u_sdio_if.sck_o",
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"oe": "1'b1"
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},
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"alt1": {
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"inputs": [],
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"do": "1'b0",
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"oe": "1'b0"
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}
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},
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{
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"pin": 1,
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"alt0": {
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"inputs": [
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"u_sdio_if.cmd_di_i"
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],
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"do": "u_sdio_if.cmd_do_o",
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"oe": "u_sdio_if.cmd_oe_o"
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},
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"alt1": {
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"inputs": [],
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"do": "1'b0",
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"oe": "1'b0"
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}
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},
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{
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"pin": 2,
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"alt0": {
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"inputs": [
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"u_sdio_if.dat_di_i[0]"
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],
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"do": "u_sdio_if.dat_do_o[0]",
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"oe": "u_sdio_if.dat_oe_o[0]"
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},
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"alt1": {
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"inputs": [],
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"do": "1'b0",
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"oe": "1'b0"
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}
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},
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{
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"pin": 3,
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"alt0": {
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"inputs": [
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"u_sdio_if.dat_di_i[1]"
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],
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"do": "u_sdio_if.dat_do_o[1]",
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"oe": "u_sdio_if.dat_oe_o[1]"
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},
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"alt1": {
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"inputs": [],
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"do": "1'b0",
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"oe": "1'b0"
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}
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},
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{
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"pin": 4,
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"alt0": {
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"inputs": [
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"u_sdio_if.dat_di_i[2]"
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],
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"do": "u_sdio_if.dat_do_o[2]",
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"oe": "u_sdio_if.dat_oe_o[2]"
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},
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"alt1": {
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"inputs": [],
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"do": "1'b0",
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"oe": "1'b0"
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}
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},
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{
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"pin": 5,
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"alt0": {
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"inputs": [
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"u_sdio_if.dat_di_i[3]"
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],
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"do": "u_sdio_if.dat_do_o[3]",
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"oe": "u_sdio_if.dat_oe_o[3]"
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},
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"alt1": {
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"inputs": [],
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"do": "1'b0",
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"oe": "1'b0"
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}
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},
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{
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"pin": 6,
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"alt0": {
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"inputs": [],
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"do": "1'b0",
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"oe": "1'b0"
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},
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"alt1": {
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"inputs": [],
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"do": "1'b0",
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"oe": "1'b0"
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}
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},
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{
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"pin": 7,
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"alt0": {
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"inputs": [],
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"do": "1'b0",
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"oe": "1'b0"
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},
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"alt1": {
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"inputs": [],
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"do": "1'b0",
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"oe": "1'b0"
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}
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},
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{
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"pin": 8,
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"alt0": {
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"inputs": [],
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"do": "u_uart0_if.tx_o",
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"oe": "1'b1"
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},
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"alt1": {
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"inputs": [],
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"do": "u_pwm_if.pwm_o[0]",
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"oe": "u_pwm_if.oe_o[0]"
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}
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},
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{
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"pin": 9,
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"alt0": {
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"inputs": [
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"u_uart0_if.rx_i"
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],
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"do": "1'b0",
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"oe": "1'b0"
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},
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"alt1": {
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"inputs": [],
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"do": "u_pwm_if.pwm_o[1]",
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"oe": "u_pwm_if.oe_o[1]"
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}
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},
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{
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"pin": 10,
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"alt0": {
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"inputs": [
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"u_i2c0_if.scl_i"
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],
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"do": "u_i2c0_if.scl_o",
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"oe": "u_i2c0_if.scl_oe_o"
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},
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"alt1": {
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"inputs": [],
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"do": "u_pwm_if.pwm_o[2]",
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"oe": "u_pwm_if.oe_o[2]"
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}
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},
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{
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"pin": 11,
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"alt0": {
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"inputs": [
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"u_i2c0_if.sda_i"
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],
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"do": "u_i2c0_if.sda_o",
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"oe": "u_i2c0_if.sda_oe_o"
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},
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"alt1": {
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"inputs": [],
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"do": "u_pwm_if.pwm_o[3]",
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"oe": "u_pwm_if.oe_o[3]"
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}
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},
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{
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"pin": 12,
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"alt0": {
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"inputs": [],
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"do": "u_i2s_if.sclk_o",
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"oe": "1'b1"
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},
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"alt1": {
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"inputs": [
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"u_dvp_if.dat_i[0]"
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],
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"do": "1'b0",
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"oe": "1'b0"
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}
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},
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{
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"pin": 13,
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"alt0": {
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"inputs": [],
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"do": "u_i2s_if.lrck_o",
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"oe": "1'b1"
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},
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"alt1": {
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"inputs": [
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"u_dvp_if.dat_i[1]"
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],
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"do": "1'b0",
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"oe": "1'b0"
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}
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},
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{
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"pin": 14,
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"alt0": {
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"inputs": [],
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"do": "u_i2s_if.dacdat_o",
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"oe": "1'b1"
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},
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"alt1": {
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"inputs": [
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"u_dvp_if.dat_i[2]"
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],
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"do": "1'b0",
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"oe": "1'b0"
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}
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},
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{
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"pin": 15,
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"alt0": {
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"inputs": [
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"u_i2s_if.adcdat_i"
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],
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"do": "1'b0",
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"oe": "1'b0"
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},
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"alt1": {
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"inputs": [
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"u_dvp_if.dat_i[3]"
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],
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"do": "1'b0",
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"oe": "1'b0"
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}
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},
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{
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"pin": 16,
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"alt0": {
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"inputs": [],
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"do": "u_i2s_if.mclk_o",
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"oe": "1'b1"
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},
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"alt1": {
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"inputs": [
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"u_dvp_if.dat_i[4]"
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],
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"do": "1'b0",
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"oe": "1'b0"
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}
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},
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{
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"pin": 17,
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"alt0": {
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"inputs": [
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"s_audio_pad_clk"
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],
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"do": "1'b0",
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"oe": "1'b0"
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},
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"alt1": {
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"inputs": [
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"u_dvp_if.dat_i[5]"
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],
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"do": "1'b0",
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"oe": "1'b0"
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}
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},
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{
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"pin": 18,
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"alt0": {
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"inputs": [],
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"do": "u_pwm_if.pwm_o[0]",
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"oe": "u_pwm_if.oe_o[0]"
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},
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"alt1": {
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"inputs": [
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"u_dvp_if.dat_i[6]"
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],
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"do": "1'b0",
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"oe": "1'b0"
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}
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},
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{
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"pin": 19,
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"alt0": {
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"inputs": [],
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"do": "u_pwm_if.pwm_o[1]",
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"oe": "u_pwm_if.oe_o[1]"
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},
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"alt1": {
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"inputs": [
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"u_dvp_if.dat_i[7]"
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],
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"do": "1'b0",
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"oe": "1'b0"
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}
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},
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{
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"pin": 20,
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"alt0": {
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"inputs": [],
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"do": "u_pwm_if.pwm_o[2]",
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"oe": "u_pwm_if.oe_o[2]"
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},
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"alt1": {
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"inputs": [
|
|
"u_dvp_if.pclk_i"
|
|
],
|
|
"do": "1'b0",
|
|
"oe": "1'b0"
|
|
}
|
|
},
|
|
{
|
|
"pin": 21,
|
|
"alt0": {
|
|
"inputs": [],
|
|
"do": "u_pwm_if.pwm_o[3]",
|
|
"oe": "u_pwm_if.oe_o[3]"
|
|
},
|
|
"alt1": {
|
|
"inputs": [
|
|
"u_dvp_if.href_i"
|
|
],
|
|
"do": "1'b0",
|
|
"oe": "1'b0"
|
|
}
|
|
},
|
|
{
|
|
"pin": 22,
|
|
"alt0": {
|
|
"inputs": [
|
|
"u_pwm_if.fault_i"
|
|
],
|
|
"do": "1'b0",
|
|
"oe": "1'b0"
|
|
},
|
|
"alt1": {
|
|
"inputs": [
|
|
"u_dvp_if.vsync_i"
|
|
],
|
|
"do": "1'b0",
|
|
"oe": "1'b0"
|
|
}
|
|
},
|
|
{
|
|
"pin": 23,
|
|
"alt0": {
|
|
"inputs": [
|
|
"u_pwm_if.sync_i"
|
|
],
|
|
"do": "1'b0",
|
|
"oe": "1'b0"
|
|
},
|
|
"alt1": {
|
|
"inputs": [],
|
|
"do": "s_clkout",
|
|
"oe": "s_clkout_enable"
|
|
}
|
|
},
|
|
{
|
|
"pin": 24,
|
|
"alt0": {
|
|
"inputs": [
|
|
"u_pwm_if.capture_i[0]"
|
|
],
|
|
"do": "1'b0",
|
|
"oe": "1'b0"
|
|
},
|
|
"alt1": {
|
|
"inputs": [],
|
|
"do": "1'b0",
|
|
"oe": "1'b0"
|
|
}
|
|
},
|
|
{
|
|
"pin": 25,
|
|
"alt0": {
|
|
"inputs": [
|
|
"u_pwm_if.capture_i[1]"
|
|
],
|
|
"do": "1'b0",
|
|
"oe": "1'b0"
|
|
},
|
|
"alt1": {
|
|
"inputs": [],
|
|
"do": "1'b0",
|
|
"oe": "1'b0"
|
|
}
|
|
},
|
|
{
|
|
"pin": 26,
|
|
"alt0": {
|
|
"inputs": [],
|
|
"do": "u_ws2812_if.dat_o",
|
|
"oe": "1'b1"
|
|
},
|
|
"alt1": {
|
|
"inputs": [],
|
|
"do": "1'b0",
|
|
"oe": "1'b0"
|
|
}
|
|
},
|
|
{
|
|
"pin": 27,
|
|
"alt0": {
|
|
"inputs": [],
|
|
"do": "1'b0",
|
|
"oe": "1'b0"
|
|
},
|
|
"alt1": {
|
|
"inputs": [],
|
|
"do": "1'b0",
|
|
"oe": "1'b0"
|
|
}
|
|
},
|
|
{
|
|
"pin": 28,
|
|
"alt0": {
|
|
"inputs": [],
|
|
"do": "s_clkout",
|
|
"oe": "s_clkout_enable"
|
|
},
|
|
"alt1": {
|
|
"inputs": [],
|
|
"do": "1'b0",
|
|
"oe": "1'b0"
|
|
}
|
|
},
|
|
{
|
|
"pin": 29,
|
|
"alt0": {
|
|
"inputs": [],
|
|
"do": "xpi.nss_o[1]",
|
|
"oe": "1'b1"
|
|
},
|
|
"alt1": {
|
|
"inputs": [],
|
|
"do": "1'b0",
|
|
"oe": "1'b0"
|
|
}
|
|
},
|
|
{
|
|
"pin": 30,
|
|
"alt0": {
|
|
"inputs": [],
|
|
"do": "xpi.nss_o[2]",
|
|
"oe": "1'b1"
|
|
},
|
|
"alt1": {
|
|
"inputs": [],
|
|
"do": "1'b0",
|
|
"oe": "1'b0"
|
|
}
|
|
},
|
|
{
|
|
"pin": 31,
|
|
"alt0": {
|
|
"inputs": [],
|
|
"do": "xpi.nss_o[3]",
|
|
"oe": "1'b1"
|
|
},
|
|
"alt1": {
|
|
"inputs": [],
|
|
"do": "1'b0",
|
|
"oe": "1'b0"
|
|
}
|
|
}
|
|
],
|
|
"dma_request_mask": "0x39ff",
|
|
"private_crypto": {
|
|
"banks": 6,
|
|
"bank_bytes": 4096,
|
|
"macro_instance": "u_soc.u_crypto.u_storage.gen_bank[{bank}].gen_macro.u_sram.u_mem",
|
|
"clock_domain": "peripheral",
|
|
"logical_domain": "PCLK"
|
|
}
|
|
}
|