mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
6cff6102a4
- Implemented module to handle debug reset requests, ensuring proper synchronization with the AHB-Lite bridge. - Created to integrate JTAG-DTM and Debug Module, facilitating abstract command exposure. - Updated and modules to include JTAG interface signals. - Enhanced the development environment with scripts for running debug sessions using OpenOCD and GDB. - Added tests for management debug reset functionality and JTAG integration, ensuring correct behavior under various scenarios. - Updated SDC generation to include JTAG clock domain and port requirements. - Modified various scripts to support new debug features and ensure compatibility with the Hazard3 architecture.
43 lines
1.2 KiB
Python
43 lines
1.2 KiB
Python
"""Directed reset-sequencing test for the management Hazard3 debug path."""
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from __future__ import annotations
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import shutil
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import subprocess
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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def test_management_debug_reset_waits_for_the_ahbl_bridge(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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simulation = tmp_path / "mgmt_debug_reset_tb"
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sources = (
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ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv",
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ROOT / "rtl/managed/clusterip/common/rtl/clkrst/rst_sync.sv",
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ROOT / "rtl/mini/top/mgmt_debug_reset.sv",
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ROOT / "tests/rtl/mgmt_debug_reset_tb.sv",
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)
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subprocess.run(
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[
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iverilog,
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"-g2012",
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"-DSV_ASSRT_DISABLE",
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f"-I{ROOT / 'rtl/managed/clusterip/common/rtl'}",
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"-s",
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"mgmt_debug_reset_tb",
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"-o",
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str(simulation),
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*(str(source) for source in sources),
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],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "management debug reset test passed" in result.stdout
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