mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
2840d22e96
- Updated to integrate a coefficient engine and additional signals for coefficient handling. - Modified to include a coefficient engine, enhancing the encoding process with new signals. - Improved to validate generated blocks against expected values and added timeout handling. - Introduced for testing SRAM wrappers in JPEG workspace. - Enhanced test coverage in to reject invalid STA net drivers. - Updated to ensure proper coverage of canonical domains in timing contracts. - Added a new test for JPEG coefficient engine in . - Improved memory map tests in to validate public active MMIO regions. - Enhanced management core specification tests in to verify high-performance core specifications. - Added behavioral-only checks in to exclude synthesis and netlist consumers. - Updated SDRAM tests in to track active firmware memory. - Enhanced STA constraints tests in to cover current clock domains and net drivers.
486 lines
16 KiB
Python
486 lines
16 KiB
Python
"""Directed verification for the configurable native-AXI4 on-chip SRAM."""
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from __future__ import annotations
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import os
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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import pytest
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ROOT = Path(__file__).resolve().parents[1]
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CAPACITIES_KIB = (4, 16, 32, 64, 128)
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@pytest.mark.parametrize("capacity_kib", CAPACITIES_KIB)
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def test_onchip_ram_axi4_capacity_protocol_and_performance(
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tmp_path: Path, capacity_kib: int
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) -> None:
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verilator = shutil.which("verilator")
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if verilator is None:
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return
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generated = tmp_path / "memory_map"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
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"--map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(generated),
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"--have-sram-if",
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"YES",
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"--sram-size-kib",
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str(capacity_kib),
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],
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check=True,
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)
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output = tmp_path / f"onchip_ram_{capacity_kib}"
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ccache_tmp = tmp_path / "ccache"
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ccache_tmp.mkdir()
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subprocess.run(
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[
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verilator,
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"--binary",
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"--timing",
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"-Wno-fatal",
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"--top-module",
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"onchip_ram_tb",
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f"-GCapacityKiB={capacity_kib}",
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"+define+PDK_BEHAV",
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"+define+SV_ASSRT_DISABLE",
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"-I" + str(generated / "rtl"),
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"-I" + str(ROOT / "rtl/mini/top"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/interface"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_addr_gen.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/tech/ram.sv"),
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str(ROOT / "rtl/tech/tc_sram.sv"),
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str(ROOT / "rtl/mini/top/onchip_ram_reg.sv"),
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str(ROOT / "rtl/mini/top/onchip_ram.sv"),
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str(ROOT / "tests/rtl/onchip_ram_tb.sv"),
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"-Mdir",
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str(tmp_path / "obj"),
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"-o",
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str(output),
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],
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check=True,
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text=True,
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capture_output=True,
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env={
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**os.environ,
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"CCACHE_DIR": str(ccache_tmp),
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"CCACHE_TEMPDIR": str(ccache_tmp),
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},
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)
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result = subprocess.run([output], check=True, text=True, capture_output=True)
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assert f"on-chip SRAM AXI4 test passed capacity_kib={capacity_kib}" in result.stdout
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@pytest.mark.parametrize("capacity_kib", (4, 32))
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def test_onchip_ram_native_axi64_width_ids_and_lanes(
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tmp_path: Path, capacity_kib: int
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) -> None:
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verilator = shutil.which("verilator")
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if verilator is None:
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return
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generated = tmp_path / "memory_map"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
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"--map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(generated),
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"--have-sram-if",
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"YES",
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"--sram-size-kib",
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str(capacity_kib),
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],
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check=True,
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)
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output = tmp_path / f"onchip_ram64_{capacity_kib}"
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ccache_tmp = tmp_path / "ccache64"
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ccache_tmp.mkdir()
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subprocess.run(
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[
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verilator,
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"--binary",
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"--timing",
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"-Wno-fatal",
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"--top-module",
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"onchip_ram64_tb",
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f"-GCapacityKiB={capacity_kib}",
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"+define+PDK_BEHAV",
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"+define+SV_ASSRT_DISABLE",
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"-I" + str(generated / "rtl"),
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"-I" + str(ROOT / "rtl/mini/top"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/interface"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_addr_gen.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/tech/ram.sv"),
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str(ROOT / "rtl/tech/tc_sram.sv"),
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str(ROOT / "rtl/mini/top/onchip_ram_reg.sv"),
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str(ROOT / "rtl/mini/top/onchip_ram.sv"),
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str(ROOT / "tests/rtl/onchip_ram64_tb.sv"),
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"-Mdir",
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str(tmp_path / "obj64"),
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"-o",
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str(output),
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],
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check=True,
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text=True,
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capture_output=True,
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env={
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**os.environ,
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"CCACHE_DIR": str(ccache_tmp),
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"CCACHE_TEMPDIR": str(ccache_tmp),
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},
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)
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result = subprocess.run([output], check=True, text=True, capture_output=True)
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assert "native AXI64 on-chip SRAM test passed" in result.stdout
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def test_absent_onchip_ram_reports_capability_and_decode_errors(tmp_path: Path) -> None:
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verilator = shutil.which("verilator")
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if verilator is None:
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return
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generated = tmp_path / "memory_map"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
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"--map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(generated),
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"--have-sram-if",
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"NO",
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],
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check=True,
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)
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output = tmp_path / "onchip_ram_absent"
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ccache_tmp = tmp_path / "ccache-absent"
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ccache_tmp.mkdir()
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subprocess.run(
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[
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verilator,
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"--binary",
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"--timing",
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"-Wno-fatal",
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"--top-module",
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"onchip_ram_absent_tb",
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"+define+SV_ASSRT_DISABLE",
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"-I" + str(generated / "rtl"),
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"-I" + str(ROOT / "rtl/mini/top"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/interface"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_addr_gen.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/tech/ram.sv"),
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str(ROOT / "rtl/tech/tc_sram.sv"),
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str(ROOT / "rtl/mini/top/onchip_ram_reg.sv"),
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str(ROOT / "rtl/mini/top/onchip_ram.sv"),
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str(ROOT / "tests/rtl/onchip_ram_absent_tb.sv"),
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"-Mdir",
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str(tmp_path / "obj-absent"),
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"-o",
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str(output),
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],
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check=True,
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text=True,
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capture_output=True,
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env={
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**os.environ,
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"CCACHE_DIR": str(ccache_tmp),
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"CCACHE_TEMPDIR": str(ccache_tmp),
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},
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)
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result = subprocess.run([output], check=True, text=True, capture_output=True)
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assert "absent on-chip SRAM test passed" in result.stdout
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def test_ihp130_wrapper_uses_functional_1024x32_macro(tmp_path: Path) -> None:
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verilator = shutil.which("verilator")
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if verilator is None:
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return
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output = tmp_path / "tc_sram_ihp130"
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ccache_tmp = tmp_path / "ccache-ihp130"
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ccache_tmp.mkdir()
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subprocess.run(
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[
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verilator,
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"--binary",
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"--timing",
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"-Wno-fatal",
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"--top-module",
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"tc_sram_1024x32_tb",
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"+define+PDK_IHP130",
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"+define+HAVE_SRAM_MACRO",
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"+define+FUNCTIONAL",
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"+define+SYNTHESIS",
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str(
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ROOT / "physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/"
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"RM_IHPSG13_1P_core_behavioral_bm_bist.v"
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),
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str(
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ROOT / "physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/"
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"RM_IHPSG13_1P_1024x32_c2_bm_bist.v"
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),
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str(ROOT / "rtl/tech/tc_sram.sv"),
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str(ROOT / "tests/rtl/tc_sram_1024x32_tb.sv"),
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"-Mdir",
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str(tmp_path / "obj-ihp130"),
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"-o",
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str(output),
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],
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check=True,
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text=True,
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capture_output=True,
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env={
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**os.environ,
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"CCACHE_DIR": str(ccache_tmp),
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"CCACHE_TEMPDIR": str(ccache_tmp),
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},
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)
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result = subprocess.run([output], check=True, text=True, capture_output=True)
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assert "1024x32 SRAM wrapper test passed" in result.stdout
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wrapper = (ROOT / "rtl/tech/tc_sram.sv").read_text(encoding="utf-8")
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assert "RM_IHPSG13_1P_1024x32_c2_bm_bist" in wrapper
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assert "RM_IHPSG13_1P_1024x64_c2_bm_bist" not in wrapper
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@pytest.mark.parametrize("macro", (False, True))
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def test_jpeg_workspace_sram_wrappers(tmp_path: Path, macro: bool) -> None:
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verilator = shutil.which("verilator")
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if verilator is None:
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return
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output = tmp_path / ("jpeg_workspace_macro" if macro else "jpeg_workspace_behavioral")
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ccache_tmp = tmp_path / ("ccache-jpeg-macro" if macro else "ccache-jpeg-behavioral")
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ccache_tmp.mkdir()
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command = [
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verilator,
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"--binary",
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"--timing",
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"-Wno-fatal",
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"--top-module",
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"tc_sram_jpeg_workspace_tb",
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]
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if macro:
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sram_root = (
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ROOT / "physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog"
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)
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command.extend(
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[
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"+define+PDK_IHP130",
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"+define+HAVE_SRAM_MACRO",
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"+define+FUNCTIONAL",
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"+define+SYNTHESIS",
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str(sram_root / "RM_IHPSG13_1P_core_behavioral_bm_bist.v"),
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str(sram_root / "RM_IHPSG13_2P_core_behavioral_ideal.v"),
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str(sram_root / "RM_IHPSG13_1P_64x64_c2_bm_bist.v"),
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str(sram_root / "RM_IHPSG13_2P_64x32_c2.v"),
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]
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)
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command.extend(
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[
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str(ROOT / "rtl/tech/tc_sram.sv"),
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str(ROOT / "tests/rtl/tc_sram_jpeg_workspace_tb.sv"),
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"-Mdir",
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str(tmp_path / ("obj-jpeg-macro" if macro else "obj-jpeg-behavioral")),
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"-o",
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str(output),
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]
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)
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subprocess.run(
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command,
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check=True,
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text=True,
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capture_output=True,
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env={
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**os.environ,
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"CCACHE_DIR": str(ccache_tmp),
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"CCACHE_TEMPDIR": str(ccache_tmp),
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},
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)
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result = subprocess.run([output], check=True, text=True, capture_output=True)
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assert "JPEG SRAM workspace wrapper test passed" in result.stdout
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def test_ics55_wrapper_preserves_active_low_controls_and_byte_masks(tmp_path: Path) -> None:
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verilator = shutil.which("verilator")
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if verilator is None:
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return
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output = tmp_path / "tc_sram_ics55"
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ccache_tmp = tmp_path / "ccache-ics55"
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ccache_tmp.mkdir()
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subprocess.run(
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[
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verilator,
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"--binary",
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"--timing",
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"-Wno-fatal",
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"--top-module",
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"tc_sram_1024x32_tb",
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"+define+PDK_ICS55",
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"+define+HAVE_SRAM_MACRO",
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str(ROOT / "tests/rtl/ics55_onchip_sram_stub.sv"),
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str(ROOT / "rtl/tech/tc_sram.sv"),
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str(ROOT / "tests/rtl/tc_sram_1024x32_tb.sv"),
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"-Mdir",
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str(tmp_path / "obj-ics55"),
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"-o",
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str(output),
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],
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check=True,
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text=True,
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capture_output=True,
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env={
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**os.environ,
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"CCACHE_DIR": str(ccache_tmp),
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"CCACHE_TEMPDIR": str(ccache_tmp),
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},
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)
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result = subprocess.run([output], check=True, text=True, capture_output=True)
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assert "1024x32 SRAM wrapper test passed" in result.stdout
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@pytest.mark.parametrize(
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("pdk", "model"),
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(
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("GF180", "gf180_sram_sim_cells.sv"),
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("SKY130", "sky130_sram_sim_cells.sv"),
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),
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)
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def test_open_pdk_sram_wrappers_preserve_depth_and_byte_masks(
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tmp_path: Path, pdk: str, model: str
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) -> None:
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verilator = shutil.which("verilator")
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if verilator is None:
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return
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output = tmp_path / f"tc_sram_{pdk.lower()}"
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ccache_tmp = tmp_path / f"ccache-{pdk.lower()}"
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ccache_tmp.mkdir()
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subprocess.run(
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[
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verilator,
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"--binary",
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"--timing",
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"-Wno-fatal",
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"--top-module",
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"tc_sram_1024x32_tb",
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f"+define+PDK_{pdk}",
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"+define+HAVE_SRAM_MACRO",
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"+define+SV_ASSRT_DISABLE",
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/tech/ram.sv"),
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str(ROOT / "rtl/tech" / model),
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str(ROOT / "rtl/tech/tc_sram.sv"),
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str(ROOT / "tests/rtl/tc_sram_1024x32_tb.sv"),
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"-Mdir",
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str(tmp_path / f"obj-{pdk.lower()}"),
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"-o",
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str(output),
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],
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check=True,
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text=True,
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capture_output=True,
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env={
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**os.environ,
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"CCACHE_DIR": str(ccache_tmp),
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"CCACHE_TEMPDIR": str(ccache_tmp),
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},
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)
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result = subprocess.run([output], check=True, text=True, capture_output=True)
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assert "1024x32 SRAM wrapper test passed" in result.stdout
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def test_native_axi4_burst_reaches_peak_and_removes_bridge_overhead(tmp_path: Path) -> None:
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verilator = shutil.which("verilator")
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if verilator is None:
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return
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|
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generated = tmp_path / "memory_map"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
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"--map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(generated),
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"--have-sram-if",
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"YES",
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"--sram-size-kib",
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"4",
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],
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check=True,
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)
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output = tmp_path / "onchip_ram_perf"
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ccache_tmp = tmp_path / "ccache-perf"
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ccache_tmp.mkdir()
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subprocess.run(
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[
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verilator,
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"--binary",
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"--timing",
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"-Wno-fatal",
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"--top-module",
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"onchip_ram_perf_tb",
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"+define+PDK_BEHAV",
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"+define+SV_ASSRT_DISABLE",
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"-I" + str(generated / "rtl"),
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"-I" + str(ROOT / "rtl/mini/top"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/interface"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv"),
|
|
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ram_if.sv"),
|
|
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_addr_gen.sv"),
|
|
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
|
|
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/xchecker.sv"),
|
|
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"),
|
|
str(ROOT / "rtl/managed/clusterip/common/rtl/tech/ram.sv"),
|
|
str(ROOT / "rtl/tech/tc_sram.sv"),
|
|
str(ROOT / "rtl/mini/top/axi42ram.sv"),
|
|
str(ROOT / "rtl/mini/top/onchip_ram_reg.sv"),
|
|
str(ROOT / "rtl/mini/top/onchip_ram.sv"),
|
|
str(ROOT / "tests/rtl/onchip_ram_perf_tb.sv"),
|
|
"-Mdir",
|
|
str(tmp_path / "obj-perf"),
|
|
"-o",
|
|
str(output),
|
|
],
|
|
check=True,
|
|
text=True,
|
|
capture_output=True,
|
|
env={
|
|
**os.environ,
|
|
"CCACHE_DIR": str(ccache_tmp),
|
|
"CCACHE_TEMPDIR": str(ccache_tmp),
|
|
},
|
|
)
|
|
result = subprocess.run([output], check=True, text=True, capture_output=True)
|
|
assert "on-chip SRAM burst cycles native=16 legacy=18" in result.stdout
|