mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
952b060a70
Integrate RNG, CRC, WS2812, Crypto, I2S master and the SDIO private AXI owner on SAFE24. Preserve the 128 KiB main SRAM and six private Crypto macros, add product-specific DMA assignments and reject unsupported SDK operations.
Correct APB read strobes, I2S receive assembly and SDIO command timing, backpressure and descriptor retirement. Add pin-level workloads, source-bound evidence checks and publication/commercial consumer compatibility.
Validation of the final P6 worktree: 1726 pytest tests passed with one optional pypdf skip (exit 0, 4021.61 seconds; terminal session 36439). Both PDKs passed both RTL simulators, netlist boot and 38-macro binding checks. Shared formal, Mini compatibility and software/source quality gates passed.
Evidence remains attributed to the retained dirty-worktree snapshots based on b3b30a72cd under build/ics55-tiny-2026-10-12-11-50-2eb98c0e1fae/meta/tiny-r2-p6/. Timing is negative and warning observations are not promoted. This commit does not accept P6, qualify physical operation or enable P7.
124 lines
3.2 KiB
Systemverilog
124 lines
3.2 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module i2s_recv (
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input logic clk_i,
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input logic rst_n_i,
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input logic sclk_pos_i,
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input logic lrck_i,
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input logic bitmode_i,
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input logic adcdat_i,
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output logic [23:0] data_o,
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output logic done_o
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);
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logic s_lrck_dely_d, s_lrck_dely_q;
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logic s_lrck_trg;
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logic [4:0] s_bit_cnt_d, s_bit_cnt_q;
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logic [4:0] s_bit_num;
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logic s_done_d, s_done_q;
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logic [23:0] s_recv_data_d, s_recv_data_q;
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logic [23:0] s_data_d, s_data_q;
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assign s_bit_num = bitmode_i ? 5'd23 : 5'd15;
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assign data_o = s_data_q;
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assign done_o = s_done_q;
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assign s_lrck_trg = lrck_i ^ s_lrck_dely_q;
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assign s_lrck_dely_d = lrck_i;
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dffer #(
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.DATA_WIDTH(1)
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) u_lrck_dely_dffer (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.en_i (sclk_pos_i),
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.dat_i (s_lrck_dely_d),
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.dat_o (s_lrck_dely_q)
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);
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always_comb begin
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s_bit_cnt_d = s_bit_cnt_q;
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if (s_lrck_trg) s_bit_cnt_d = '0;
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else if (s_bit_cnt_q < s_bit_num) begin
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s_bit_cnt_d = s_bit_cnt_q + 1'b1;
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end
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end
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dffer #(
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.DATA_WIDTH(5)
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) u_bit_cnt_dffer (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.en_i (sclk_pos_i),
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.dat_i (s_bit_cnt_d),
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.dat_o (s_bit_cnt_q)
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);
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always_comb begin
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s_recv_data_d = s_recv_data_q;
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if (s_lrck_trg) begin
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s_recv_data_d = '0;
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end else if (s_bit_cnt_q < s_bit_num) begin
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if (bitmode_i) begin
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s_recv_data_d[23:0] = {s_recv_data_q[22:0], adcdat_i};
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end else begin
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s_recv_data_d[23:16] = s_recv_data_q[23:16];
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s_recv_data_d[15:0] = {s_recv_data_q[14:0], adcdat_i};
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end
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end
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end
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dffer #(
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.DATA_WIDTH(24)
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) u_recv_data_dffer (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.en_i (sclk_pos_i),
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.dat_i (s_recv_data_d),
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.dat_o (s_recv_data_q)
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);
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// I2S changes LRCK one bit before the next sample's MSB. The bit
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// sampled on that transition is the current sample's LSB, not the next
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// sample's first bit. Publish completion after data_o has captured it.
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assign s_done_d = sclk_pos_i && s_lrck_trg;
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dffr #(
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.DATA_WIDTH(1)
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) u_done_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_done_d),
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.dat_o (s_done_q)
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);
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always_comb begin
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s_data_d = s_data_q;
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if (s_lrck_trg) begin
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if (bitmode_i) s_data_d = {s_recv_data_q[22:0], adcdat_i};
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else s_data_d = {8'd0, s_recv_data_q[14:0], adcdat_i};
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end
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end
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dffer #(
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.DATA_WIDTH(24)
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) u_data_dffer (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.en_i (sclk_pos_i),
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.dat_i (s_data_d),
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.dat_o (s_data_q)
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);
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endmodule
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