mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
952b060a70
Integrate RNG, CRC, WS2812, Crypto, I2S master and the SDIO private AXI owner on SAFE24. Preserve the 128 KiB main SRAM and six private Crypto macros, add product-specific DMA assignments and reject unsupported SDK operations.
Correct APB read strobes, I2S receive assembly and SDIO command timing, backpressure and descriptor retirement. Add pin-level workloads, source-bound evidence checks and publication/commercial consumer compatibility.
Validation of the final P6 worktree: 1726 pytest tests passed with one optional pypdf skip (exit 0, 4021.61 seconds; terminal session 36439). Both PDKs passed both RTL simulators, netlist boot and 38-macro binding checks. Shared formal, Mini compatibility and software/source quality gates passed.
Evidence remains attributed to the retained dirty-worktree snapshots based on b3b30a72cd under build/ics55-tiny-2026-10-12-11-50-2eb98c0e1fae/meta/tiny-r2-p6/. Timing is negative and warning observations are not promoted. This commit does not accept P6, qualify physical operation or enable P7.
88 lines
2.3 KiB
Systemverilog
88 lines
2.3 KiB
Systemverilog
`timescale 1ns / 1ps
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module tiny_r2_p6_bridge_tb;
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logic clk_i = 0, rst_n_i = 0;
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always #5 clk_i = !clk_i;
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.USER_WIDTH(1)
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) axi (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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apb4_if apb (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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tiny_axi42apb4 u_dut (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.axi4 (axi),
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.apb4 (apb)
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);
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assign apb.pready = apb.psel && apb.penable;
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assign apb.prdata = 32'h13579bdf;
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// A strict APB4 receiver rejects nonzero read strobes independently of PWRITE.
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assign apb.pslverr = apb.psel && apb.penable && !apb.pwrite && apb.pstrb != 0;
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task automatic write_read(input logic [3:0] mask);
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@(negedge clk_i);
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axi.awvalid = 1;
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do @(posedge clk_i); while (!axi.awready);
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@(negedge clk_i);
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axi.awvalid = 0;
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axi.wvalid = 1;
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axi.wstrb = mask;
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do @(posedge clk_i); while (!axi.wready);
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@(negedge clk_i);
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axi.wvalid = 0;
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do @(posedge clk_i); while (!apb.penable);
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if (!apb.pwrite || apb.pstrb !== mask) $fatal(1, "SIM_TEST_FAIL lost write byte lanes");
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do @(posedge clk_i); while (!axi.bvalid);
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if (axi.bresp != 0) $fatal(1, "SIM_TEST_FAIL APB write response");
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@(negedge clk_i);
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axi.arvalid = 1;
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do @(posedge clk_i); while (!axi.arready);
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@(negedge clk_i);
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axi.arvalid = 0;
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do @(posedge clk_i); while (!axi.rvalid);
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if (axi.rresp != 0 || axi.rdata !== 32'h13579bdf || !axi.rlast)
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$fatal(1, "SIM_TEST_FAIL stale write strobes corrupted APB read");
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@(negedge clk_i);
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endtask
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initial begin
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axi.awvalid = 0;
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axi.awaddr = 'h10007000;
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axi.awlen = 0;
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axi.awsize = 2;
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axi.awburst = 1;
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axi.awlock = 0;
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axi.awid = 0;
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axi.wvalid = 0;
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axi.wdata = 'h12345678;
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axi.wstrb = 0;
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axi.wlast = 1;
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axi.bready = 1;
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axi.arvalid = 0;
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axi.araddr = 'h10007008;
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axi.arlen = 0;
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axi.arsize = 2;
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axi.arburst = 1;
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axi.arlock = 0;
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axi.arid = 0;
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axi.rready = 1;
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repeat (4) @(negedge clk_i);
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rst_n_i = 1;
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write_read(15);
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write_read(1);
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write_read(3);
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write_read(10);
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$display("SIM_TEST_PASS Tiny P6 APB read strobes");
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$finish;
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end
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initial begin
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#100000;
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$fatal(1, "SIM_TEST_TIMEOUT P6 APB strobes");
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end
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endmodule
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