mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
97335b9df1
- Updated Makefile to include a check for the RNG metadata script and added a dependency for it. - Modified memory_map.json to change the user access level of APB_RNG to 'none'. - Updated clusterip filelist to include new RNG source files. - Adjusted generate_soc_topology.py to replace the reserved IRQ with the RNG IRQ. - Updated soc_topology.json to reflect the new RNG interrupt configuration. - Added RNG source files to software.mk for compilation. - Enhanced ip_apb_wrapper.sv to instantiate the RNG core and connect it to the APB interface. - Updated test_memory_map.py to ensure SOC_ADDR_IS_APB_RNG is not defined. - Modified test_script_tools.py to ensure dry runs do not write filelists. - Updated test_soc_topology.py to verify the new RNG IRQ and adjust the user IRQ mask.
77 lines
7.2 KiB
JSON
77 lines
7.2 KiB
JSON
{
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"schema_version": 1,
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"cpu_reset": "0x00000000",
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"sysctrl_registers": [
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{"symbol": "CORESEL", "offset": "0x00"},
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{"symbol": "IPSEL", "offset": "0x04"},
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{"symbol": "PLL_CFG", "offset": "0x08"},
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{"symbol": "PLL_CMD", "offset": "0x0C"},
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{"symbol": "FAULT_STATUS", "offset": "0x10"},
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{"symbol": "FAULT_ADDR", "offset": "0x14"},
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{"symbol": "FAULT_COUNT", "offset": "0x18"},
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{"symbol": "PLL_STATUS", "offset": "0x1C"},
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{"symbol": "USER_CORE_RESET", "offset": "0x20"},
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{"symbol": "USER_CORE_STATUS", "offset": "0x24"},
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{"symbol": "FAULT_MASTER", "offset": "0x28"},
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{"symbol": "FAULT_DETAIL", "offset": "0x2C"},
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{"symbol": "PERF_CTRL", "offset": "0x40"},
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{"symbol": "PERF_MGMT_WAIT_LO", "offset": "0x44"},
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{"symbol": "PERF_MGMT_WAIT_HI", "offset": "0x48"},
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{"symbol": "PERF_USER_WAIT_LO", "offset": "0x4C"},
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{"symbol": "PERF_USER_WAIT_HI", "offset": "0x50"},
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{"symbol": "PERF_DMA_WAIT_LO", "offset": "0x54"},
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{"symbol": "PERF_DMA_WAIT_HI", "offset": "0x58"},
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{"symbol": "PERF_RIBP_WAIT_LO", "offset": "0x5C"},
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{"symbol": "PERF_RIBP_WAIT_HI", "offset": "0x60"},
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{"symbol": "PERF_APB_WAIT_LO", "offset": "0x64"},
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{"symbol": "PERF_APB_WAIT_HI", "offset": "0x68"},
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{"symbol": "PERF_SDRAM_WAIT_LO", "offset": "0x6C"},
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{"symbol": "PERF_SDRAM_WAIT_HI", "offset": "0x70"},
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{"symbol": "PERF_PSRAM_WAIT_LO", "offset": "0x74"},
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{"symbol": "PERF_PSRAM_WAIT_HI", "offset": "0x78"},
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{"symbol": "PERF_FLASH_WAIT_LO", "offset": "0x7C"},
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{"symbol": "PERF_FLASH_WAIT_HI", "offset": "0x80"},
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{"symbol": "TEST_STATUS", "offset": "0x84"}
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],
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"regions": [
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{"symbol": "FLASH", "base": "0x00000000", "size": "0x01000000", "route": "ribp", "kind": "active", "public": true, "linker": "FLASH", "user_access": "ro", "burst": "incr4"},
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{"symbol": "RIBP_GPIO", "base": "0x10000000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "RIBP_UART0", "base": "0x10001000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "RIBP_TIM0", "base": "0x10002000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "RIBP_TIM1", "base": "0x10003000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "RIBP_PSRAM", "base": "0x10004000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
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{"symbol": "RIBP_SPISD", "base": "0x10005000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "RIBP_I2C0", "base": "0x10006000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "RIBP_I2S", "base": "0x10007000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "RIBP_WS2812", "base": "0x10008000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "RIBP_XPI", "base": "0x10009000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
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{"symbol": "RIBP_DMA", "base": "0x1000A000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
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{"symbol": "RIBP_SYSCTRL", "base": "0x1000B000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
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{"symbol": "RIBP_CLINT", "base": "0x10020000", "size": "0x00010000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
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{"symbol": "RIBP_SDRAM", "base": "0x1000D000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
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{"symbol": "RIBP_DVP", "base": "0x1000E000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "RIBP_SDIO", "base": "0x1000F000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
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{"symbol": "RIBP_OPIPSRAM", "base": "0x10010000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
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{"symbol": "RIBP_I2C1", "base": "0x10011000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "RIBP_GA", "base": "0x10012000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
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{"symbol": "RIBP_APU", "base": "0x10013000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
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{"symbol": "RIBP_GPIO_ADMIN", "base": "0x10014000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
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{"symbol": "APB_ARCHINFO", "base": "0x20000000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "ro"},
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{"symbol": "APB_RNG", "base": "0x20001000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "none"},
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{"symbol": "APB_UART1", "base": "0x20002000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "APB_PWM", "base": "0x20003000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "APB_PS2", "base": "0x20004000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "APB_RTC", "base": "0x20005000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "APB_WDG", "base": "0x20006000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "none"},
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{"symbol": "APB_CRC", "base": "0x20007000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "APB_TMR", "base": "0x20008000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "APB_USER_IP", "base": "0x2000F000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
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{"symbol": "SRAM", "base": "0x30000000", "size": "0x00020000", "route": "ram", "kind": "active", "public": true, "linker": "SRAM", "user_access": "rw", "burst": "incr4"},
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{"symbol": "SDRAM", "base": "0x38000000", "size": "0x02000000", "route": "ribp", "kind": "active", "public": true, "linker": "SDRAM", "user_access": "rw", "burst": "incr4"},
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{"symbol": "PSRAM", "base": "0x40000000", "size": "0x00800000", "route": "ribp", "kind": "active", "public": true, "linker": "PSRAM", "user_access": "rw", "burst": "incr4"},
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{"symbol": "OPIPSRAM", "base": "0x48000000", "size": "0x08000000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
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{"symbol": "XPI", "base": "0x50000000", "size": "0x10000000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw", "burst": "incr4"},
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{"symbol": "SPISD", "base": "0x60000000", "size": "0x40000000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw", "burst": "incr4"}
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]
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}
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