mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
8266791cfc
- Updated to include I2C1 in IRQ bindings. - Modified to increase IRQ group width and add I2C1 interrupt. - Enhanced to include I2C formal properties and adjust timeouts. - Added I2C-related source files to the formal verification flow. - Updated DMA wrapper in to handle I2C DMA signals. - Created a new testbench for I2C functionality verification. - Implemented I2C helper functions in for testing. - Added I2C tests in to validate controller behavior and recovery. - Updated existing tests to accommodate changes in DMA and IRQ handling.
67 lines
2.1 KiB
Python
67 lines
2.1 KiB
Python
"""Directed I2C V2 controller, FIFO, error, timeout, and recovery tests."""
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from __future__ import annotations
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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def test_i2c_v2_controller_and_recovery_contract(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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common = ROOT / "rtl/managed/clusterip/common/rtl"
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serial = ROOT / "rtl/ip/ribp/serial"
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cluster_i2c = ROOT / "rtl/managed/clusterip/i2c/rtl"
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source_list = tmp_path / "i2c.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{common}",
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f"+incdir+{common / 'interface'}",
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f"+incdir+{common / 'utils'}",
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f"+incdir+{common / 'cdc'}",
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f"+incdir+{serial}",
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str(common / "interface/ribp_if.sv"),
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str(common / "utils/register.sv"),
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str(common / "utils/fifo.sv"),
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str(common / "cdc/cdc_sync.sv"),
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str(cluster_i2c / "i2c_if.sv"),
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str(serial / "i2c_filter.sv"),
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str(serial / "i2c_core.sv"),
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str(serial / "i2c_reg.sv"),
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str(serial / "ribp_i2c.sv"),
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str(ROOT / "tests/rtl/i2c_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "i2c_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "i2c_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "i2c_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "I2C V2 transfer, error, stretch, arbitration, and recovery test passed" in result.stdout
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