mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
98eb8ebad6
- Implemented tests for AXI4 async bridge functionality, including transfer and warm flush scenarios. - Added tests for AXI4 data crossbar to validate concurrent outstanding requests and ACL handling. - Introduced clock frequency monitor tests to ensure detection of clock stop and restart events. - Developed tests for extension DMA master to verify copy operations, tail strobe behavior, and timeout handling. - Created tests for HP lifecycle controller to validate drain, flush, and forced reset functionalities. - Updated existing test scripts to include new RTL components and ensure proper simulation configurations.
272 lines
8.3 KiB
Systemverilog
272 lines
8.3 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// SPDX-License-Identifier: MulanPSL-2.0
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module axi4_async_bridge #(
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parameter int unsigned AddrWidth = 32,
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parameter int unsigned DataWidth = 32,
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parameter int unsigned IdWidth = 1,
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parameter int unsigned UserWidth = 1,
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parameter int unsigned FifoDepth = 4
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) (
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// verilog_format: off -- preserve the source/destination clock boundary columns
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input logic src_clk_i,
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input logic src_rst_n_i,
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input logic dst_clk_i,
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input logic dst_rst_n_i,
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input logic clear_i,
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output logic clear_busy_o,
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output logic [7:0] epoch_o,
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axi4_if.slave src_axi4,
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axi4_if.master dst_axi4
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// verilog_format: on
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);
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localparam int unsigned StrbWidth = DataWidth / 8;
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localparam int unsigned AwWidth = IdWidth + AddrWidth + 8 + 3 + 2 + 1 + 4 + 3 + 4 + 4 + UserWidth;
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localparam int unsigned WWidth = DataWidth + StrbWidth + 1 + UserWidth;
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localparam int unsigned BWidth = IdWidth + 2 + UserWidth;
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localparam int unsigned ArWidth = AwWidth;
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localparam int unsigned RWidth = IdWidth + DataWidth + 2 + 1 + UserWidth;
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logic [AwWidth-1:0] s_aw_src_data;
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logic [AwWidth-1:0] s_aw_dst_data;
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logic [ WWidth-1:0] s_w_src_data;
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logic [ WWidth-1:0] s_w_dst_data;
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logic [ BWidth-1:0] s_b_dst_data;
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logic [ BWidth-1:0] s_b_src_data;
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logic [ArWidth-1:0] s_ar_src_data;
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logic [ArWidth-1:0] s_ar_dst_data;
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logic [ RWidth-1:0] s_r_dst_data;
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logic [ RWidth-1:0] s_r_src_data;
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logic s_clear_src;
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logic s_clear_dst;
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logic s_clear_q;
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logic s_clear_dst_q;
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logic s_clear_src_pulse;
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logic s_clear_dst_pulse;
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logic [7:0] s_epoch_d, s_epoch_q;
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logic s_aw_src_clear_busy, s_aw_dst_clear_busy;
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logic s_w_src_clear_busy, s_w_dst_clear_busy;
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logic s_b_src_clear_busy, s_b_dst_clear_busy;
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logic s_ar_src_clear_busy, s_ar_dst_clear_busy;
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logic s_r_src_clear_busy, s_r_dst_clear_busy;
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cdc_sync #(
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.STAGE (2),
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.DATA_WIDTH(1)
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) u_clear_src_sync (
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.clk_i (src_clk_i),
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.rst_n_i(src_rst_n_i),
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.dat_i (clear_i),
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.dat_o (s_clear_src)
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);
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cdc_sync #(
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.STAGE (2),
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.DATA_WIDTH(1)
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) u_clear_sync (
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.clk_i (dst_clk_i),
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.rst_n_i(dst_rst_n_i),
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.dat_i (clear_i),
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.dat_o (s_clear_dst)
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);
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assign s_clear_src_pulse = s_clear_src && !s_clear_q;
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assign s_clear_dst_pulse = s_clear_dst && !s_clear_dst_q;
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assign s_aw_src_data = {
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src_axi4.awid,
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src_axi4.awaddr,
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src_axi4.awlen,
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src_axi4.awsize,
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src_axi4.awburst,
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src_axi4.awlock,
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src_axi4.awcache,
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src_axi4.awprot,
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src_axi4.awqos,
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src_axi4.awregion,
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src_axi4.awuser
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};
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assign {
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dst_axi4.awid,
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dst_axi4.awaddr,
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dst_axi4.awlen,
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dst_axi4.awsize,
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dst_axi4.awburst,
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dst_axi4.awlock,
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dst_axi4.awcache,
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dst_axi4.awprot,
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dst_axi4.awqos,
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dst_axi4.awregion,
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dst_axi4.awuser
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} = s_aw_dst_data;
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cdc_fifo_warm_flush #(
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.DATA_WIDTH (AwWidth),
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.BUFFER_DEPTH(FifoDepth)
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) u_aw_fifo (
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.src_clk_i (src_clk_i),
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.src_rst_n_i (src_rst_n_i),
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.src_clear_i (s_clear_src_pulse),
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.src_clear_busy_o(s_aw_src_clear_busy),
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.src_data_i (s_aw_src_data),
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.src_valid_i (src_axi4.awvalid),
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.src_ready_o (src_axi4.awready),
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.dst_clk_i (dst_clk_i),
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.dst_rst_n_i (dst_rst_n_i),
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.dst_clear_busy_o(s_aw_dst_clear_busy),
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.dst_data_o (s_aw_dst_data),
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.dst_valid_o (dst_axi4.awvalid),
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.dst_ready_i (dst_axi4.awready)
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);
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assign s_w_src_data = {src_axi4.wdata, src_axi4.wstrb, src_axi4.wlast, src_axi4.wuser};
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assign {dst_axi4.wdata, dst_axi4.wstrb, dst_axi4.wlast, dst_axi4.wuser} = s_w_dst_data;
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cdc_fifo_warm_flush #(
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.DATA_WIDTH (WWidth),
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.BUFFER_DEPTH(FifoDepth)
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) u_w_fifo (
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.src_clk_i (src_clk_i),
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.src_rst_n_i (src_rst_n_i),
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.src_clear_i (s_clear_src_pulse),
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.src_clear_busy_o(s_w_src_clear_busy),
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.src_data_i (s_w_src_data),
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.src_valid_i (src_axi4.wvalid),
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.src_ready_o (src_axi4.wready),
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.dst_clk_i (dst_clk_i),
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.dst_rst_n_i (dst_rst_n_i),
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.dst_clear_busy_o(s_w_dst_clear_busy),
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.dst_data_o (s_w_dst_data),
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.dst_valid_o (dst_axi4.wvalid),
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.dst_ready_i (dst_axi4.wready)
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);
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assign s_b_dst_data = {dst_axi4.bid, dst_axi4.bresp, dst_axi4.buser};
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assign {src_axi4.bid, src_axi4.bresp, src_axi4.buser} = s_b_src_data;
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cdc_fifo_warm_flush #(
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.DATA_WIDTH (BWidth),
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.BUFFER_DEPTH(FifoDepth)
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) u_b_fifo (
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.src_clk_i (dst_clk_i),
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.src_rst_n_i (dst_rst_n_i),
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.src_clear_i (s_clear_dst_pulse),
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.src_clear_busy_o(s_b_dst_clear_busy),
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.src_data_i (s_b_dst_data),
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.src_valid_i (dst_axi4.bvalid),
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.src_ready_o (dst_axi4.bready),
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.dst_clk_i (src_clk_i),
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.dst_rst_n_i (src_rst_n_i),
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.dst_clear_busy_o(s_b_src_clear_busy),
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.dst_data_o (s_b_src_data),
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.dst_valid_o (src_axi4.bvalid),
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.dst_ready_i (src_axi4.bready)
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);
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assign s_ar_src_data = {
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src_axi4.arid,
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src_axi4.araddr,
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src_axi4.arlen,
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src_axi4.arsize,
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src_axi4.arburst,
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src_axi4.arlock,
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src_axi4.arcache,
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src_axi4.arprot,
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src_axi4.arqos,
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src_axi4.arregion,
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src_axi4.aruser
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};
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assign {
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dst_axi4.arid,
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dst_axi4.araddr,
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dst_axi4.arlen,
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dst_axi4.arsize,
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dst_axi4.arburst,
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dst_axi4.arlock,
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dst_axi4.arcache,
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dst_axi4.arprot,
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dst_axi4.arqos,
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dst_axi4.arregion,
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dst_axi4.aruser
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} = s_ar_dst_data;
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cdc_fifo_warm_flush #(
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.DATA_WIDTH (ArWidth),
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.BUFFER_DEPTH(FifoDepth)
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) u_ar_fifo (
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.src_clk_i (src_clk_i),
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.src_rst_n_i (src_rst_n_i),
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.src_clear_i (s_clear_src_pulse),
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.src_clear_busy_o(s_ar_src_clear_busy),
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.src_data_i (s_ar_src_data),
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.src_valid_i (src_axi4.arvalid),
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.src_ready_o (src_axi4.arready),
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.dst_clk_i (dst_clk_i),
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.dst_rst_n_i (dst_rst_n_i),
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.dst_clear_busy_o(s_ar_dst_clear_busy),
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.dst_data_o (s_ar_dst_data),
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.dst_valid_o (dst_axi4.arvalid),
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.dst_ready_i (dst_axi4.arready)
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);
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assign s_r_dst_data = {
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dst_axi4.rid, dst_axi4.rdata, dst_axi4.rresp, dst_axi4.rlast, dst_axi4.ruser
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};
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assign {src_axi4.rid, src_axi4.rdata, src_axi4.rresp, src_axi4.rlast,
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src_axi4.ruser} = s_r_src_data;
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cdc_fifo_warm_flush #(
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.DATA_WIDTH (RWidth),
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.BUFFER_DEPTH(FifoDepth)
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) u_r_fifo (
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.src_clk_i (dst_clk_i),
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.src_rst_n_i (dst_rst_n_i),
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.src_clear_i (s_clear_dst_pulse),
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.src_clear_busy_o(s_r_dst_clear_busy),
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.src_data_i (s_r_dst_data),
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.src_valid_i (dst_axi4.rvalid),
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.src_ready_o (dst_axi4.rready),
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.dst_clk_i (src_clk_i),
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.dst_rst_n_i (src_rst_n_i),
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.dst_clear_busy_o(s_r_src_clear_busy),
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.dst_data_o (s_r_src_data),
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.dst_valid_o (src_axi4.rvalid),
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.dst_ready_i (src_axi4.rready)
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);
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assign clear_busy_o = s_aw_src_clear_busy || s_aw_dst_clear_busy ||
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s_w_src_clear_busy || s_w_dst_clear_busy ||
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s_b_src_clear_busy || s_b_dst_clear_busy ||
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s_ar_src_clear_busy || s_ar_dst_clear_busy ||
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s_r_src_clear_busy || s_r_dst_clear_busy;
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assign s_epoch_d = (s_clear_src_pulse && !clear_busy_o) ? s_epoch_q + 1'b1 : s_epoch_q;
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assign epoch_o = s_epoch_q;
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always_ff @(posedge src_clk_i or negedge src_rst_n_i) begin
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if (!src_rst_n_i) begin
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s_clear_q <= 1'b0;
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s_epoch_q <= '0;
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end else begin
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s_clear_q <= s_clear_src;
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s_epoch_q <= s_epoch_d;
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end
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end
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always_ff @(posedge dst_clk_i or negedge dst_rst_n_i) begin
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if (!dst_rst_n_i) begin
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s_clear_dst_q <= 1'b0;
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end else begin
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s_clear_dst_q <= s_clear_dst;
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end
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end
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`ifndef SYNTHESIS
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initial begin
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if ((AddrWidth < 1) || (DataWidth < 8) || ((DataWidth % 8) != 0) ||
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(IdWidth < 1) || (UserWidth < 1) || (FifoDepth < 2) ||
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((FifoDepth & (FifoDepth - 1)) != 0)) begin
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$fatal(1, "axi4_async_bridge: invalid interface or FIFO parameters");
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end
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end
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`endif
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endmodule
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