mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
98eb8ebad6
- Implemented tests for AXI4 async bridge functionality, including transfer and warm flush scenarios. - Added tests for AXI4 data crossbar to validate concurrent outstanding requests and ACL handling. - Introduced clock frequency monitor tests to ensure detection of clock stop and restart events. - Developed tests for extension DMA master to verify copy operations, tail strobe behavior, and timeout handling. - Created tests for HP lifecycle controller to validate drain, flush, and forced reset functionalities. - Updated existing test scripts to include new RTL components and ensure proper simulation configurations.
231 lines
7.4 KiB
Systemverilog
231 lines
7.4 KiB
Systemverilog
`timescale 1ns / 1ps
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module axi4_data_crossbar_tb;
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localparam int NumMasters = 8;
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localparam int NumTargets = 6;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic idle_o;
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logic [ 7:0] outstanding_read_o;
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logic [ 7:0] outstanding_write_o;
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logic fault_valid_o;
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logic [ 2:0] fault_master_o;
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logic [ 2:0] fault_target_o;
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logic [31:0] fault_addr_o;
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logic fault_write_o;
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logic [ 3:0] fault_reason_o;
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(64),
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.ID_WIDTH (6),
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.USER_WIDTH(1)
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) masters[NumMasters] (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(64),
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.ID_WIDTH (6),
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.USER_WIDTH(1)
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) targets[NumTargets] (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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always #5 clk_i = ~clk_i;
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initial begin
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repeat (500) @(posedge clk_i);
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$fatal(1, "AXI4 data crossbar test timed out");
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end
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axi4_data_crossbar u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.block_new_i (1'b0),
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.recovery_i (1'b0),
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.mem_pad_mode_i (2'd1),
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.ext_h_read_base_i (32'h3000_0000),
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.ext_h_read_limit_i (32'h4FFF_FFFF),
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.ext_h_write_base_i (32'h3000_0000),
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.ext_h_write_limit_i(32'h4FFF_FFFF),
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.masters (masters),
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.targets (targets),
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.idle_o (idle_o),
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.outstanding_read_o (outstanding_read_o),
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.outstanding_write_o(outstanding_write_o),
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.fault_valid_o (fault_valid_o),
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.fault_master_o (fault_master_o),
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.fault_target_o (fault_target_o),
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.fault_addr_o (fault_addr_o),
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.fault_write_o (fault_write_o),
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.fault_reason_o (fault_reason_o)
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);
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task automatic issue_master1_read(input logic [5:0] id, input logic [31:0] addr);
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begin
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@(negedge clk_i);
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masters[1].arid = id;
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masters[1].araddr = addr;
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masters[1].arvalid = 1'b1;
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do @(posedge clk_i); while (!masters[1].arready);
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@(negedge clk_i);
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masters[1].arvalid = 1'b0;
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end
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endtask
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task automatic return_target0_read(input logic [5:0] id, input logic [63:0] data);
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begin
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@(negedge clk_i);
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targets[0].rid = id;
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targets[0].rdata = data;
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targets[0].rresp = 2'b00;
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targets[0].rlast = 1'b1;
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targets[0].rvalid = 1'b1;
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do @(posedge clk_i); while (!targets[0].rready);
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@(negedge clk_i);
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targets[0].rvalid = 1'b0;
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end
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endtask
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task automatic return_target1_read(input logic [5:0] id, input logic [63:0] data);
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begin
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@(negedge clk_i);
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targets[1].rid = id;
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targets[1].rdata = data;
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targets[1].rresp = 2'b00;
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targets[1].rlast = 1'b1;
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targets[1].rvalid = 1'b1;
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do @(posedge clk_i); while (!targets[1].rready);
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@(negedge clk_i);
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targets[1].rvalid = 1'b0;
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end
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endtask
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`define INIT_MASTER(index) \
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masters[index].awid = '0; \
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masters[index].awaddr = '0; \
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masters[index].awlen = '0; \
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masters[index].awsize = 3'd3; \
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masters[index].awburst = 2'b01; \
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masters[index].awlock = 1'b0; \
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masters[index].awcache = '0; \
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masters[index].awprot = '0; \
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masters[index].awqos = '0; \
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masters[index].awregion = '0; \
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masters[index].awuser = '0; \
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masters[index].awvalid = 1'b0; \
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masters[index].wdata = '0; \
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masters[index].wstrb = '0; \
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masters[index].wlast = 1'b1; \
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masters[index].wuser = '0; \
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masters[index].wvalid = 1'b0; \
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masters[index].bready = 1'b1; \
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masters[index].arid = '0; \
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masters[index].araddr = '0; \
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masters[index].arlen = '0; \
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masters[index].arsize = 3'd3; \
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masters[index].arburst = 2'b01; \
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masters[index].arlock = 1'b0; \
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masters[index].arcache = '0; \
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masters[index].arprot = '0; \
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masters[index].arqos = '0; \
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masters[index].arregion = '0; \
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masters[index].aruser = '0; \
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masters[index].arvalid = 1'b0; \
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masters[index].rready = 1'b1;
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`define INIT_TARGET(index) \
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targets[index].awready = 1'b1; \
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targets[index].wready = 1'b1; \
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targets[index].bid = '0; \
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targets[index].bresp = '0; \
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targets[index].buser = '0; \
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targets[index].bvalid = 1'b0; \
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targets[index].arready = 1'b1; \
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targets[index].rid = '0; \
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targets[index].rdata = '0; \
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targets[index].rresp = '0; \
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targets[index].rlast = 1'b1; \
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targets[index].ruser = '0; \
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targets[index].rvalid = 1'b0;
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initial begin
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`INIT_MASTER(0)
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`INIT_MASTER(1)
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`INIT_MASTER(2)
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`INIT_MASTER(3)
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`INIT_MASTER(4)
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`INIT_MASTER(5)
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`INIT_MASTER(6)
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`INIT_MASTER(7)
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`INIT_TARGET(0)
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`INIT_TARGET(1)
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`INIT_TARGET(2)
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`INIT_TARGET(3)
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`INIT_TARGET(4)
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`INIT_TARGET(5)
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repeat (3) @(posedge clk_i);
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rst_n_i = 1'b1;
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issue_master1_read(6'b001_000, 32'h3000_0000);
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issue_master1_read(6'b001_001, 32'h3800_0000);
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if (outstanding_read_o != 8'd2 || idle_o) begin
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$fatal(1, "different-target reads were not tracked concurrently");
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end
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@(negedge clk_i);
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masters[1].arid = 6'b001_000;
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masters[1].araddr = 32'h4000_0000;
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masters[1].arvalid = 1'b1;
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#1;
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if (masters[1].arready) $fatal(1, "same source ID was accepted before completion");
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masters[1].arvalid = 1'b0;
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fork
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return_target1_read(6'b001_001, 64'h2222_2222_2222_2222);
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begin
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wait (masters[1].rvalid);
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if ((masters[1].rid != 6'b001_001) || (masters[1].rdata != 64'h2222_2222_2222_2222)) begin
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$fatal(1, "out-of-order different-ID response was misrouted");
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end
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end
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join
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return_target0_read(6'b001_000, 64'h1111_1111_1111_1111);
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@(negedge clk_i);
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if (!idle_o || (outstanding_read_o != 8'd0)) begin
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$fatal(1, "read completion did not drain the crossbar");
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end
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@(negedge clk_i);
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masters[6].arid = 6'b110_000;
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masters[6].araddr = 32'h3000_0000;
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masters[6].arvalid = 1'b1;
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do @(posedge clk_i); while (!masters[6].arready);
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#1;
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if (!fault_valid_o || (fault_master_o != 3'd6) ||
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(fault_reason_o != 4'd3) || fault_write_o) begin
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$fatal(1, "reserved-master ACL fault attribution mismatch");
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end
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@(negedge clk_i);
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masters[6].arvalid = 1'b0;
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targets[5].rid = 6'b110_000;
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targets[5].rresp = 2'b10;
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targets[5].rlast = 1'b1;
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targets[5].rvalid = 1'b1;
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do @(posedge clk_i); while (!targets[5].rready);
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@(negedge clk_i);
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targets[5].rvalid = 1'b0;
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$display("AXI4 data crossbar concurrency and ACL test passed");
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$finish;
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end
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`undef INIT_MASTER
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`undef INIT_TARGET
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endmodule
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