mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
9c706ba0ff
- Updated paths in test files to reflect new directory structure for RTL and script files. - Changed references from rtl/mini to rtl/ip and scripts/rtl where applicable. - Added a new test file for Tiny product isolation, ensuring independent ABI and bus acceptance. - Enhanced tests for memory map generation and protocol contracts for Tiny architecture. - Ensured that all tests are aligned with the latest directory structure and naming conventions.
110 lines
3.8 KiB
Systemverilog
110 lines
3.8 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "onchip_ram_define.svh"
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module onchip_ram_reg #(
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parameter bit Present = 1'b1,
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parameter int unsigned CapacityKiB = 128,
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parameter int unsigned DataBytes = 4
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) (
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// verilog_format: off -- preserve the register input grouping
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input logic clk_i,
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input logic rst_n_i,
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apb4_if.slave apb4,
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input logic [31:0] perf_read_requests_i,
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input logic [31:0] perf_write_requests_i,
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input logic [31:0] perf_read_beats_i,
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input logic [31:0] perf_write_beats_i,
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input logic [31:0] perf_stall_cycles_i,
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input logic [31:0] perf_error_responses_i
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// verilog_format: on
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);
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localparam logic [31:0] IpId = 32'h5352_414D;
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localparam logic [31:0] IpVersion = 32'h0001_0000;
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localparam int unsigned BankBytes = 4096;
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localparam int unsigned BankCount = CapacityKiB / 4;
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localparam logic [31:0] Capability =
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32'(DataBytes << `APB4_ONCHIP_RAM__CAP_DATA_BYTES_LSB) |
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32'(16 << `APB4_ONCHIP_RAM__CAP_MAX_BEATS_LSB) |
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32'h0000_007E | 32'(Present);
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logic s_req;
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logic s_aligned;
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logic s_offset_valid;
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logic s_access_err;
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logic s_ready_d;
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logic s_ready_q;
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logic s_resp_err_d;
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logic s_resp_err_q;
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logic [31:0] s_rdata_d;
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logic [31:0] s_rdata_q;
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assign s_req = apb4.psel && apb4.penable && !s_ready_q;
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assign s_aligned = apb4.paddr[1:0] == 2'b00;
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assign s_access_err = !s_aligned || apb4.pwrite || !s_offset_valid;
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assign s_ready_d = s_req;
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assign s_resp_err_d = s_req && s_access_err;
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assign apb4.pready = s_ready_q;
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assign apb4.prdata = s_rdata_q;
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assign apb4.pslverr = s_resp_err_q;
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always_comb begin
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s_offset_valid = 1'b1;
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s_rdata_d = 32'd0;
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unique case (apb4.paddr[11:0])
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`APB4_ONCHIP_RAM__IP_ID: s_rdata_d = IpId;
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`APB4_ONCHIP_RAM__IP_VERSION: s_rdata_d = IpVersion;
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`APB4_ONCHIP_RAM__CAPABILITY: s_rdata_d = Capability;
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`APB4_ONCHIP_RAM__MEMORY_BYTES: s_rdata_d = Present ? 32'(CapacityKiB * 1024) : 32'd0;
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`APB4_ONCHIP_RAM__BANK_COUNT: s_rdata_d = Present ? 32'(BankCount) : 32'd0;
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`APB4_ONCHIP_RAM__BANK_BYTES: s_rdata_d = 32'(BankBytes);
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`APB4_ONCHIP_RAM__PERF_READ_REQUESTS: s_rdata_d = perf_read_requests_i;
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`APB4_ONCHIP_RAM__PERF_WRITE_REQUESTS: s_rdata_d = perf_write_requests_i;
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`APB4_ONCHIP_RAM__PERF_READ_BEATS: s_rdata_d = perf_read_beats_i;
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`APB4_ONCHIP_RAM__PERF_WRITE_BEATS: s_rdata_d = perf_write_beats_i;
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`APB4_ONCHIP_RAM__PERF_STALL_CYCLES: s_rdata_d = perf_stall_cycles_i;
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`APB4_ONCHIP_RAM__PERF_ERROR_RESPONSES: s_rdata_d = perf_error_responses_i;
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default: begin
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s_offset_valid = 1'b0;
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s_rdata_d = 32'd0;
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end
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endcase
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end
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dffr #(
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.DATA_WIDTH(1)
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) u_ready_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_ready_d),
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.dat_o (s_ready_q)
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);
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dffr #(
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.DATA_WIDTH(1)
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) u_resp_err_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_resp_err_d),
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.dat_o (s_resp_err_q)
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);
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dffer #(
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.DATA_WIDTH(32)
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) u_rdata_dffer (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.en_i (s_req),
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.dat_i (s_rdata_d),
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.dat_o (s_rdata_q)
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);
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endmodule
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