mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
9c706ba0ff
- Updated paths in test files to reflect new directory structure for RTL and script files. - Changed references from rtl/mini to rtl/ip and scripts/rtl where applicable. - Added a new test file for Tiny product isolation, ensuring independent ABI and bus acceptance. - Enhanced tests for memory map generation and protocol contracts for Tiny architecture. - Ensured that all tests are aligned with the latest directory structure and naming conventions.
200 lines
8.7 KiB
Makefile
200 lines
8.7 KiB
Makefile
GENERATED_FL_DIR := $(FLOW_FILELIST_DIR)
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MEMORY_MAP_SOURCE := $(RTL_PATH)/address_map/memory_map.json
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MEMORY_MAP_SCRIPT := $(ROOT_PATH)/scripts/rtl/generate_memory_map.py
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MEMORY_MAP_DIR := $(VARIANT_ROOT)/generated/memory_map
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MEMORY_MAP_STAMP := $(MEMORY_MAP_DIR)/.stamp
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MEMORY_MAP_RTL_DIR := $(MEMORY_MAP_DIR)/rtl
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MEMORY_MAP_C_DIR := $(MEMORY_MAP_DIR)/include
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MEMORY_MAP_LINKER_DIR := $(MEMORY_MAP_DIR)/linker
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MEMORY_MAP_FILELIST := $(MEMORY_MAP_DIR)/memory_map.fl
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PIN_MAP_SOURCE := $(RTL_PATH)/pin_map/pin_map.json
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PIN_MAP_SCRIPT := $(ROOT_PATH)/scripts/rtl/generate_pin_map.py
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PIN_MAP_DIR := $(VARIANT_ROOT)/generated/pin_map
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PIN_MAP_STAMP := $(PIN_MAP_DIR)/.stamp
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PIN_MAP_FILELIST := $(PIN_MAP_DIR)/pin_map.fl
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SOC_TOPOLOGY_SOURCE := $(RTL_PATH)/integration/soc_topology.json
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SOC_TOPOLOGY_SCRIPT := $(RTL_PATH)/integration/generate_soc_topology.py
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SOC_TOPOLOGY_DIR := $(VARIANT_ROOT)/generated/soc_topology
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SOC_TOPOLOGY_STAMP := $(SOC_TOPOLOGY_DIR)/.stamp
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SOC_TOPOLOGY_FILELIST := $(SOC_TOPOLOGY_DIR)/soc_topology.fl
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SOC_TOPOLOGY_INCLUDE_DIR := $(SOC_TOPOLOGY_DIR)/include
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SOC_IRQ_METADATA := $(SOC_TOPOLOGY_INCLUDE_DIR)/retrosoc/generated/irq_metadata.h
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PRODUCT_EXTENSIONS_SOURCE := $(RTL_PATH)/integration/user_extensions.json
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LEGACY_EXTENSIONS_SOURCE := $(RTL_PATH)/integration/user_extensions_legacy.json
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USER_EXTENSIONS_SOURCE := $(if $(filter MPW,$(MINI_MODE)),$(LEGACY_EXTENSIONS_SOURCE),$(PRODUCT_EXTENSIONS_SOURCE))
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USER_EXTENSIONS_SCRIPT := $(RTL_PATH)/integration/generate_user_extensions.py
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USER_EXTENSIONS_DIR := $(VARIANT_ROOT)/generated/user_extensions
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USER_EXTENSIONS_STAMP := $(USER_EXTENSIONS_DIR)/.stamp
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USER_EXTENSIONS_FILELIST := $(USER_EXTENSIONS_DIR)/user_extensions.fl
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ARCHINFO_METADATA_SCRIPT := $(ROOT_PATH)/rtl/managed/clusterip/archinfo/scripts/generate_metadata.py
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ARCHINFO_METADATA_DEPS := $(wildcard $(ARCHINFO_METADATA_SCRIPT))
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ARCHINFO_METADATA_DIR := $(VARIANT_ROOT)/generated/archinfo
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ARCHINFO_METADATA_STAMP := $(ARCHINFO_METADATA_DIR)/.stamp
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ARCHINFO_METADATA_SV := $(ARCHINFO_METADATA_DIR)/archinfo_integration_metadata.svh
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ARCHINFO_METADATA_C := $(ARCHINFO_METADATA_DIR)/archinfo_integration_metadata.h
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CLOCK_RESET_DOMAINS_SOURCE := $(RTL_PATH)/integration/clock_reset_domains.json
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CLOCK_RESET_DOMAINS_SCRIPT := $(ROOT_PATH)/scripts/check_clock_reset_domains.py
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MPW_STAMP := $(CACHE_ROOT)/stamps/mpw-$(LOCK_DIGEST).prepared
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MPW_OUTPUT_DIR := $(VARIANT_ROOT)/generated/mpw/$(SIM_TOOL_NAME)
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MPW_VARIANT_STAMP := $(MPW_OUTPUT_DIR)/.stamp
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MPW_VARIANT_DEP := $(if $(filter MPW,$(MINI_MODE)),$(MPW_VARIANT_STAMP))
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FILELIST_STAMP := $(GENERATED_FL_DIR)/.stamp
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PDK_LOCAL_FILELIST := $(GENERATED_FL_DIR)/pdk_local.fl
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FILELIST_TEMPLATES := $(sort $(wildcard $(ROOT_PATH)/rtl/filelist/pdk_*.fl) \
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$(wildcard $(RTL_PATH)/filelist/*.fl) $(RTL_PATH)/lint.msg)
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MPW_MANAGEMENT_CORE_CHECK := @test -d $(ROOT_PATH)/rtl/managed/hazard3/hdl || { \
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echo "missing $(ROOT_PATH)/rtl/managed/hazard3; run 'make setup-mpw' first" >&2; \
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exit 1; \
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}
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$(MPW_STAMP):
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@test -d $(ROOT_PATH)/rtl/managed/mpw/.git || { \
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echo "missing $(ROOT_PATH)/rtl/managed/mpw; run 'make setup-mpw' first" >&2; \
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exit 1; \
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}
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$(MPW_MANAGEMENT_CORE_CHECK)
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$(FLOW_PYTHON) $(ROOT_PATH)/scripts/prepare_mpw.py \
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--lock-file $(CACHE_ROOT)/locks/mpw-prepare.lock
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@mkdir -p $(@D)
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@touch $@
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$(MPW_VARIANT_STAMP): $(MPW_STAMP) $(LEGACY_EXTENSIONS_SOURCE) $(ROOT_PATH)/scripts/generate_mpw.py
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$(FLOW_PYTHON) $(ROOT_PATH)/scripts/generate_mpw.py --root $(ROOT_PATH) \
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--output $(MPW_OUTPUT_DIR) \
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--extensions $(LEGACY_EXTENSIONS_SOURCE) \
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--lock-file $(CACHE_ROOT)/locks/mpw.lock
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@mkdir -p $(@D)
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@touch $@
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gen_mpw_code: $(MPW_VARIANT_STAMP)
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$(MEMORY_MAP_STAMP): $(MEMORY_MAP_SOURCE) $(MEMORY_MAP_SCRIPT)
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$(FLOW_PYTHON) $(MEMORY_MAP_SCRIPT) --map $(MEMORY_MAP_SOURCE) \
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--output-dir $(MEMORY_MAP_DIR) --have-sram-if $(HAVE_SRAM_IF) \
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--sram-size-kib $(SRAM_SIZE_KIB)
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@touch $@
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memory-map: $(MEMORY_MAP_STAMP)
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check-memory-map:
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$(FLOW_PYTHON) $(MEMORY_MAP_SCRIPT) --map $(MEMORY_MAP_SOURCE) --check
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$(PIN_MAP_STAMP): $(PIN_MAP_SOURCE) $(PIN_MAP_SCRIPT)
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$(FLOW_PYTHON) $(PIN_MAP_SCRIPT) --map $(PIN_MAP_SOURCE) --output-dir $(PIN_MAP_DIR)
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@touch $@
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pin-map: $(PIN_MAP_STAMP)
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check-pin-map:
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$(FLOW_PYTHON) $(PIN_MAP_SCRIPT) --map $(PIN_MAP_SOURCE) --check
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$(SOC_TOPOLOGY_STAMP): $(SOC_TOPOLOGY_SOURCE) $(SOC_TOPOLOGY_SCRIPT) $(MEMORY_MAP_SOURCE)
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$(FLOW_PYTHON) $(SOC_TOPOLOGY_SCRIPT) --map $(SOC_TOPOLOGY_SOURCE) \
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--memory-map $(MEMORY_MAP_SOURCE) --output-dir $(SOC_TOPOLOGY_DIR) \
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--external-irq-count $(if $(filter PRODUCT,$(MINI_MODE)),62,30)
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@touch $@
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$(SOC_IRQ_METADATA): $(SOC_TOPOLOGY_STAMP)
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@test -f $@ || { echo "missing generated IRQ metadata: $@" >&2; exit 1; }
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soc-topology: $(SOC_TOPOLOGY_STAMP)
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check-soc-topology:
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$(FLOW_PYTHON) $(SOC_TOPOLOGY_SCRIPT) --map $(SOC_TOPOLOGY_SOURCE) \
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--memory-map $(MEMORY_MAP_SOURCE) --check
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$(USER_EXTENSIONS_STAMP): $(USER_EXTENSIONS_SOURCE) $(USER_EXTENSIONS_SCRIPT)
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$(FLOW_PYTHON) $(USER_EXTENSIONS_SCRIPT) --map $(USER_EXTENSIONS_SOURCE) \
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--output-dir $(USER_EXTENSIONS_DIR)
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@touch $@
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user-extensions: $(USER_EXTENSIONS_STAMP)
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check-user-extensions:
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$(FLOW_PYTHON) $(USER_EXTENSIONS_SCRIPT) --map $(USER_EXTENSIONS_SOURCE) --check
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check-archinfo-source:
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@test -f $(ARCHINFO_METADATA_SCRIPT) || { \
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echo "missing $(ARCHINFO_METADATA_SCRIPT); run 'make setup-clusterip' first" >&2; \
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exit 1; \
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}
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$(ARCHINFO_METADATA_STAMP): $(ARCHINFO_METADATA_DEPS) $(LOCK_FILE) | check-archinfo-source
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$(FLOW_PYTHON) $(ARCHINFO_METADATA_SCRIPT) --repo-root $(ROOT_PATH) --lock $(LOCK_FILE) \
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--config-digest $(CONFIG_DIGEST) $(if $(filter YES,$(BUILD_RELEASE)),--release) \
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--output-sv $(ARCHINFO_METADATA_SV) --output-c $(ARCHINFO_METADATA_C)
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@touch $@
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archinfo-metadata: $(ARCHINFO_METADATA_STAMP)
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check-clock-reset-domains:
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$(FLOW_PYTHON) $(CLOCK_RESET_DOMAINS_SCRIPT) --map $(CLOCK_RESET_DOMAINS_SOURCE) --root $(ROOT_PATH)
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$(FILELIST_STAMP): $(FILELIST_TEMPLATES) $(RTL_PATH)/script/generate_filelist.py $(LOCAL_RTL_FILES) \
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$(ROOT_PATH)/scripts/rtl/filelist.py $(MEMORY_MAP_STAMP) $(PIN_MAP_STAMP) $(SOC_TOPOLOGY_STAMP) \
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$(USER_EXTENSIONS_STAMP) $(ARCHINFO_METADATA_STAMP) \
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$(if $(filter MPW,$(MINI_MODE)),$(MPW_VARIANT_STAMP)) \
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$(if $(filter YES,$(HAVE_HP)),$(HP_GENERATED_STAMP))
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$(FLOW_PYTHON) $(RTL_PATH)/script/generate_filelist.py \
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--output-dir $(GENERATED_FL_DIR) \
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--incdir $(ARCHINFO_METADATA_DIR) \
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$(foreach source,$(LOCAL_RTL_FILES),--local-rtl-file $(source)) \
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$(foreach define,$(DEF_LIST),--define $(define))
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@touch $@
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generate_filelist: $(FILELIST_STAMP)
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# software
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include $(ROOT_PATH)/rtl/mk/software.mk
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#====================== filelist ======================
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ifeq ($(PDK), IHP130)
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PDK_FILELIST := $(GENERATED_FL_DIR)/pdk_ihp130.fl
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else ifeq ($(PDK), SKY130)
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PDK_FILELIST := $(GENERATED_FL_DIR)/pdk_sky130.fl
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else ifeq ($(PDK), ICS55)
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ifeq ($(SYNTH), YOSYS)
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PDK_FILELIST := $(GENERATED_FL_DIR)/pdk_ics55_yosys.fl
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else ifeq ($(SIMU), VERILATOR)
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PDK_FILELIST := $(GENERATED_FL_DIR)/pdk_ics55_verilator.fl
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else
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PDK_FILELIST := $(GENERATED_FL_DIR)/pdk_ics55.fl
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endif
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else ifeq ($(PDK), GF180)
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PDK_FILELIST := $(GENERATED_FL_DIR)/pdk_gf180.fl
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endif
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NET_FILELISTS := $(PDK_FILELIST) \
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$(PDK_LOCAL_FILELIST) \
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$(GENERATED_FL_DIR)/def.fl \
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$(GENERATED_FL_DIR)/sys_def.fl \
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$(GENERATED_FL_DIR)/commonip.fl \
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$(GENERATED_FL_DIR)/inc.fl \
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$(PIN_MAP_FILELIST)
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NET_FLIST := $(foreach filelist,$(NET_FILELISTS),-f $(filelist))
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RTL_FILELISTS := $(MEMORY_MAP_FILELIST) $(SOC_TOPOLOGY_FILELIST) $(USER_EXTENSIONS_FILELIST) \
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$(NET_FILELISTS) \
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$(GENERATED_FL_DIR)/clusterip.fl \
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$(GENERATED_FL_DIR)/ip.fl \
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$(GENERATED_FL_DIR)/tech.fl \
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$(GENERATED_FL_DIR)/core_hazard3.fl \
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$(if $(filter MPW,$(MINI_MODE)),$(MPW_OUTPUT_DIR)/core/core.fl,$(USER_EXTENSIONS_DIR)/legacy_core.fl) \
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$(if $(filter MPW,$(MINI_MODE)),$(MPW_OUTPUT_DIR)/ip/ip.fl,$(USER_EXTENSIONS_DIR)/legacy_ip.fl) \
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$(if $(filter YES,$(HAVE_HP)),$(HP_GENERATED_DIR)/vexiiriscv.fl) \
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$(GENERATED_FL_DIR)/top.fl
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RTL_FLIST := $(foreach filelist,$(RTL_FILELISTS),-f $(filelist))
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#====================== end ======================
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ifeq ($(SIMU), VCS)
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include $(RTL_PATH)/mk/vcs.mk
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else ifeq ($(SIMU), VERILATOR)
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include $(RTL_PATH)/mk/verilator.mk
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else ifeq ($(SIMU), IVERILOG)
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include $(RTL_PATH)/mk/iverilog.mk
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endif
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.PHONY: gen_mpw_code generate_filelist memory-map check-memory-map pin-map check-pin-map \
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soc-topology check-soc-topology user-extensions check-user-extensions \
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archinfo-metadata check-archinfo-source check-clock-reset-domains firmware |