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a2b12f911a4ee654995bb686164659584eebf133
retroSoC/rtl/rtl_style_audit.json
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maksyuki a2b12f911a feat: add RTL unit tests for NPU-P3 job execution 
This commit introduces a comprehensive set of unit tests for the NPU-P3 job execution, covering the DMA engine, job decoder, and core functionalities. The tests utilize Icarus and Verilator for simulation and include descriptor validation, fault handling, and various operational scenarios. Key features include:

- Descriptor construction and validation mirroring ABI 1.0.
- Detailed test cases for valid and invalid descriptors.
- Core testbench scenarios for various operations including convolution, pooling, and fully connected layers.
- Integration of golden model comparisons for output verification.

These tests aim to ensure robust functionality and adherence to specifications for the NPU-P3 architecture.
2026-09-19 23:36:20 +08:00

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{
"schema_version": 1,
"policy": "docs/rtl-coding-style.md",
"profile": "owned",
"review_methods": [
"automated static checks",
"tool-assisted source review",
"targeted simulation and formal source-list review"
],
"reviewed_boundary_record": {
"owner": "retroSoC RTL maintainers",
"related_commit": "7df897b03820ab4f9b48472eef4308698c9a7df4",
"expiry": "Expires before a behavior-changing or sequential-equivalence-verified refactor of an affected module.",
"removal_plan": "Use an isolated change with named validation evidence; do not treat this audit record as a warning baseline or a blanket waiver."
},
"rules": [
{
"id": "RTL-FILE",
"sections": [
2
],
"result": "compliant",
"evidence": "Primary-unit/file-name checks and canonical filelist review."
},
{
"id": "RTL-SV",
"sections": [
3
],
"result": "compliant",
"evidence": "Restricted-SystemVerilog static checks and Verible lint."
},
{
"id": "RTL-NAME",
"sections": [
4
],
"result": "compliant",
"evidence": "Full-profile naming enforcement and boundary review."
},
{
"id": "RTL-STRUCT",
"sections": [
5
],
"result": "compliant",
"evidence": "Named-connection, generate-label, one-primary-unit, and filelist checks."
},
{
"id": "RTL-COMB",
"sections": [
6
],
"result": "reviewed",
"evidence": "Combinational defaults and protocol-path source review."
},
{
"id": "RTL-SEQ",
"sections": [
6
],
"result": "reviewed",
"evidence": "Reset, enable, FSM, inferred-memory, and sequential-priority review."
},
{
"id": "RTL-WIDTH",
"sections": [
7
],
"result": "reviewed",
"evidence": "Verilator lint and width, signedness, and X/Z source review."
},
{
"id": "RTL-CDC",
"sections": [
8
],
"result": "reviewed",
"evidence": "Clock/reset-domain metadata, CDC primitive review, and targeted tests."
},
{
"id": "RTL-VERIFY",
"sections": [
9
],
"result": "reviewed",
"evidence": "Formal source-list checks, readiness checks, and directed simulations."
},
{
"id": "RTL-FMT",
"sections": [
10
],
"result": "compliant",
"evidence": "Verible format, ASCII, whitespace, line-length, and paired-directive checks."
}
],
"inventory": {
"rtl/ip/experimental": [
"apb4_gpu.sv",
"axi4f2ribp.sv",
"wb2ribp.sv"
],
"rtl/ip/interconnect": [
"axi4l2ribp.sv",
"ribp2ribp.sv",
"ribp_regslice.sv"
],
"rtl/ip/memory": [
"apb4_opipsram.sv",
"apb4_psram.sv",
"axi4_sdram.sv",
"opipsram_axi4.sv",
"opipsram_core.sv",
"opipsram_define.svh",
"opipsram_if.sv",
"opipsram_phy.sv",
"opipsram_pkg.sv",
"opipsram_protocol.sv",
"opipsram_reg.sv",
"opipsram_trx.sv",
"psram_axi4.sv",
"psram_core.sv",
"psram_define.svh",
"psram_phy.sv",
"psram_pkg.sv",
"psram_reg.sv",
"sdram_clkgen.sv",
"sdram_core.sv",
"sdram_define.svh",
"sdram_pkg.sv",
"sdram_axi4.sv",
"sdram_reg.sv"
],
"rtl/ip/multimedia": [
"apb4_apu.sv",
"apb4_ga2d.sv",
"apb4_jpeg.sv",
"apb4_npu.sv",
"apu_bitstream_engine.sv",
"apu_codec_controller.sv",
"apu_codec_sequencer.sv",
"apu_codec_transport.sv",
"apu_control_store.sv",
"apu_dma.sv",
"apu_define.svh",
"apu_entropy_engine.sv",
"apu_kernel_engine.sv",
"apu_kws_apum_profile.svh",
"apu_kws_engine.sv",
"apu_kws_model_loader.sv",
"apu_kws_rom.svh",
"apu_kws_sram_client.sv",
"apu_local_sram.sv",
"apu_microcode_loader.sv",
"apu_microcode_pkg.sv",
"apu_primitive_dispatcher.sv",
"apu_reconstruction_engine.sv",
"apu_resampler.sv",
"apu_ring_scheduler.sv",
"apu_reg.sv",
"apu_stream_router.sv",
"apu_transform_engine.sv",
"axi4s_dvp.sv",
"dvp_core.sv",
"dvp_define.svh",
"dvp_reg.sv",
"ga2d_addr_gen.sv",
"ga2d_axi4_master.sv",
"ga2d_core.sv",
"ga2d_dma.sv",
"ga2d_define.svh",
"ga2d_pixel.sv",
"ga2d_pkg.sv",
"ga2d_reg.sv",
"jpeg_bit_packer.sv",
"jpeg_bit_reader.sv",
"jpeg_block_decoder.sv",
"jpeg_block_encoder.sv",
"jpeg_byte_joiner.sv",
"jpeg_byte_unpacker.sv",
"jpeg_coefficient_engine.sv",
"jpeg_decode_core.sv",
"jpeg_define.svh",
"jpeg_dma.sv",
"jpeg_encode_core.sv",
"jpeg_entropy_decoder.sv",
"jpeg_entropy_encoder.sv",
"jpeg_header_writer.sv",
"jpeg_marker_parser.sv",
"jpeg_mcu_builder.sv",
"jpeg_mcu_reconstructor.sv",
"jpeg_pkg.sv",
"jpeg_quantizer.sv",
"jpeg_reg.sv",
"jpeg_table_cache.sv",
"jpeg_table_register_bank.sv",
"jpeg_table_store.sv",
"jpeg_transform.sv",
"npu_accumulator.sv",
"npu_control_cdc.sv",
"npu_core.sv",
"npu_define.svh",
"npu_dma.sv",
"npu_job_decoder.sv",
"npu_local_sram.sv",
"npu_mac_array.sv",
"npu_patch_packer.sv",
"npu_pkg.sv",
"npu_reg.sv",
"npu_requantizer.sv",
"npu_scheduler.sv",
"npu_vector.sv"
],
"rtl/ip/peripheral": [
"apb4_clint.sv",
"clock_ctrl_if.sv",
"apb4_dma.sv",
"apb4_gpio.sv",
"apb4_hp_mailbox.sv",
"apb4_plic.sv",
"apb4_sysctrl.sv",
"apb4_timer.sv",
"clint_core.sv",
"clint_define.svh",
"clint_if.sv",
"clint_reg.sv",
"clint_timebase.sv",
"dma_axi4_master.sv",
"dma_core.sv",
"dma_define.svh",
"dma_pkg.sv",
"dma_reg.sv",
"dma_req_if.sv",
"gpio_core.sv",
"gpio_define.svh",
"gpio_if.sv",
"gpio_reg.sv",
"hp_mailbox_define.svh",
"pll_ctrl_if.sv",
"sysctrl_core.sv",
"sysctrl_define.svh",
"sysctrl_if.sv",
"sysctrl_reg.sv",
"timer_core.sv",
"timer_define.svh",
"timer_reg.sv",
"user_gpio_if.sv"
],
"rtl/ip/serial": [
"apb4_i2c.sv",
"apb4_i2c_define.svh",
"apb4_i2s.sv",
"apb4_uart.sv",
"apb4_uart_define.svh",
"apb4_uart_rx.sv",
"apb4_uart_tx.sv",
"apb4_ws2812.sv",
"i2c_core.sv",
"i2c_filter.sv",
"i2c_if.sv",
"i2c_reg.sv",
"i2s_clkgen.sv",
"i2s_core.sv",
"i2s_define.svh",
"i2s_pkg.sv",
"i2s_recv.sv",
"i2s_reg.sv",
"i2s_send.sv",
"uart_baudgen.sv",
"uart_core.sv",
"uart_flow_ctrl.sv",
"uart_if.sv",
"uart_reg.sv",
"ws2812_core.sv",
"ws2812_define.svh",
"ws2812_if.sv",
"ws2812_reg.sv"
],
"rtl/ip/security": [
"apb4_crypto.sv",
"crypto_aes_core.sv",
"crypto_aes_engine.sv",
"crypto_define.svh",
"crypto_montgomery.sv",
"crypto_pkg.sv",
"crypto_rsa_core.sv",
"crypto_sha2_core.sv",
"crypto_sha2_engine.sv"
],
"rtl/ip/storage": [
"apb4_sdio.sv",
"apb4_spisd.sv",
"apb4_xpi.sv",
"sdio_clock.sv",
"sdio_command.sv",
"sdio_core.sv",
"sdio_crc16.sv",
"sdio_crc7.sv",
"sdio_data.sv",
"sdio_define.svh",
"sdio_dma.sv",
"sdio_dma_descriptor.sv",
"sdio_if.sv",
"sdio_pkg.sv",
"sdio_reg.sv",
"spi_if.sv",
"spisd_clock.sv",
"spisd_command.sv",
"spisd_core.sv",
"spisd_data.sv",
"spisd_define.svh",
"spisd_pkg.sv",
"spisd_reg.sv",
"xpi_clkgen.sv",
"xpi_core.sv",
"xpi_define.svh",
"xpi_if.sv",
"xpi_indirect.sv",
"xpi_mm.sv",
"xpi_pkg.sv",
"xpi_reg.sv"
],
"rtl/ip/util": [
"async_fifo.sv"
],
"rtl/ip/usb": [
"apb4_usb2.sv",
"usb2_define.svh",
"usb2_dma.sv",
"usb2_dma_descriptor.sv",
"usb2_link_domain.sv",
"usb2_packet_ram.sv",
"usb2_packet_store.sv",
"usb2_pkg.sv",
"usb2_reg.sv",
"usb2_role_controller.sv",
"usb2_scheduler.sv",
"usb2_sie_rx.sv",
"usb2_sie_tx.sv",
"usb2_transaction_engine.sv",
"usb2_ulpi_if.sv",
"usb2_ulpi_link.sv"
],
"rtl/mini/top": [
"ahbl2axi4.sv",
"ahbl2ribp.sv",
"apb4_if_bridge.sv",
"apb4_async_bridge.sv",
"apb4_periph.sv",
"apb4_system.sv",
"axi42apb4_system.sv",
"axi42apb4_periph.sv",
"axi42ram.sv",
"axi42ribp.sv",
"axi42ribp_burst.sv",
"axi4_bus.sv",
"axi4_address_gate.sv",
"axi4_async_bridge.sv",
"axi4_connector.sv",
"axi4_data_crossbar.sv",
"axi4_target_guard.sv",
"axi4_downsizer_64to32.sv",
"axi4_error_slave.sv",
"axi4_id_prefix.sv",
"axi4_interconnect.sv",
"axi4_master_idle.sv",
"axi4_mgmt_router.sv",
"axi4_upsizer_32to64.sv",
"axi4_word_bridge.sv",
"core_wrapper.sv",
"clock_config_controller.sv",
"clock_frequency_monitor.sv",
"data_plane_fault_cdc.sv",
"extension_compat.sv",
"extension_dma_master.sv",
"extension_slot.sv",
"extension_subsystem.sv",
"fabric_monitor.sv",
"gpio_pad_bridge.sv",
"hp_axi4_mux3.sv",
"hp_core_wrapper.sv",
"hp_subsystem.sv",
"hp_lifecycle_controller.sv",
"mgmt_core_wrapper.sv",
"mgmt_debug_reset.sv",
"mgmt_debug_wrapper.sv",
"memory_pad_mux.sv",
"onchip_ram_define.svh",
"onchip_ram_reg.sv",
"onchip_ram.sv",
"pll_rcu_controller.sv",
"rcu.sv",
"resource_controller.sv",
"retrosoc.sv",
"retrosoc_asic.sv",
"retrosoc_core.sv",
"rib2apb.sv",
"rib2axi4.sv",
"rib2ram.sv",
"rib2ribp.sv",
"rib_bus.sv",
"rib_defs.svh",
"rib_error_slave.sv",
"rib_if.sv",
"ribp2axi4.sv",
"ribp2rib.sv",
"ribp_arbiter2.sv",
"soc_clock_config.svh",
"soc_clock_gate.sv",
"soc_clock_reset_subsystem.sv",
"soc_common_cdc.sv",
"soc_common_fifo.sv",
"soc_data_plane.sv",
"user_core_design.sv",
"user_core_top.sv",
"user_extensions.svh",
"user_ip_design_template.sv",
"user_ip_top.sv",
"user_ip_wrapper.sv",
"axi42apb4.svh",
"axi42apb4_state.svh"
]
},
"reviewed_boundaries": [
{
"paths": [
"rtl/ip/experimental/axi4f2ribp.sv",
"rtl/ip/experimental/apb4_gpu.sv",
"rtl/ip/experimental/wb2ribp.sv"
],
"result": "inactive experimental source",
"rationale": "The modules remain primary-unit-aligned but are not active filelist inputs. Incomplete protocol behavior was not changed by style work."
},
{
"paths": [
"rtl/ip/memory/psram_core.sv",
"rtl/ip/memory/sdram_core.sv",
"rtl/ip/multimedia/dvp_core.sv",
"rtl/ip/multimedia/dvp_reg.sv",
"rtl/ip/storage/xpi_mm.sv"
],
"result": "raw sequential storage retained",
"rationale": "Reset and update priorities, SPI/SDRAM timing, or inferred-memory behavior are cycle-sensitive. Replacing these processes with Common register primitives requires a separate sequential-equivalence proof and affected protocol simulation."
},
{
"paths": [
"rtl/ip/util/async_fifo.sv"
],
"result": "retained implementation",
"rationale": "Dual-clock storage, Gray-pointer synchronization, and inferred-memory behavior cannot be replaced by single-clock Common registers without equivalence evidence."
},
{
"paths": [
"rtl/ip/usb/apb4_usb2.sv",
"rtl/ip/usb/usb2_link_domain.sv",
"rtl/ip/usb/usb2_packet_ram.sv"
],
"result": "reviewed CDC and technology-memory boundary",
"rationale": "The system/ULPI boundary uses managed request-acknowledge synchronizers, asynchronous FIFOs, level synchronizers, and event toggles. Packet RAM retains a single-port technology wrapper with SECDED encoding; replacement requires CDC and memory-equivalence evidence."
},
{
"paths": [
"rtl/mini/top/axi4_interconnect.sv"
],
"result": "retained implementation",
"rationale": "Priority-sensitive master, target, and performance state arrays remain unchanged pending separate sequential-equivalence proof."
},
{
"paths": [
"rtl/mini/top/onchip_ram.sv",
"rtl/mini/top/onchip_ram_reg.sv"
],
"result": "reviewed AXI and technology-memory boundary",
"rationale": "AXI and APB state uses Common registers; the synchronous bank array retains the stable technology wrapper and PDK SRAM pin boundary."
},
{
"paths": [
"rtl/mini/top/soc_common_cdc.sv",
"rtl/mini/top/soc_common_fifo.sv"
],
"result": "managed compatibility wrapper retained",
"rationale": "The narrow self-owned wrappers preserve required Verilator filename behavior while including managed Common source."
},
{
"paths": [
"rtl/mini/top/user_core_design.sv",
"rtl/mini/top/user_ip_design_template.sv"
],
"result": "external template compatibility retained",
"rationale": "Template interfaces remain stable for externally distributed user designs."
}
]
}
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