mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
9c706ba0ff
- Updated paths in test files to reflect new directory structure for RTL and script files. - Changed references from rtl/mini to rtl/ip and scripts/rtl where applicable. - Added a new test file for Tiny product isolation, ensuring independent ABI and bus acceptance. - Enhanced tests for memory map generation and protocol contracts for Tiny architecture. - Ensured that all tests are aligned with the latest directory structure and naming conventions.
150 lines
3.3 KiB
ArmAsm
150 lines
3.3 KiB
ArmAsm
.section .init
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.global _start
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.type _start,@function
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#include "retrosoc/arch/riscv/system_csr.h"
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#include "retrosoc/generated/memory_map.h"
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_start:
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#ifdef CSR_ENABLE
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/* Disable Global Interrupt */
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csrc CSR_MSTATUS, MSTATUS_MIE
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/* Disable all interrupts controlled by CSR MIE */
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csrw CSR_MIE, 0x0
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/* Set Trap Entry MTVEC to trap_entry */
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la t0, system_trap_entry
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csrw CSR_MTVEC, t0
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/* Direct Mode: All exceptions set pc to BASE */
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csrc CSR_MTVEC, 0x3
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#endif
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#ifndef RS_SOC_TINY
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# wait psram reset done
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la a0, _flash_wait_start
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la a1, 2000
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wait_psram_reset:
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lw t0, 0(a0)
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addi a0, a0, 4
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blt a0, a1, wait_psram_reset
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#endif
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# ===== Startup Stage 1 =====
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# init the regfile
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# zero-initialize register file
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li x1, 0
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# x2 (sp) is initialized by hardware
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la x2, _stack_point
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10, 0
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li x11, 0
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li x12, 0
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li x13, 0
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li x14, 0
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li x15, 0
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#if ISA_RV32I || ISA_RV32IM
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li x16, 0
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li x17, 0
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li x18, 0
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li x19, 0
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li x20, 0
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li x21, 0
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li x22, 0
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li x23, 0
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li x24, 0
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li x25, 0
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li x26, 0
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li x27, 0
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li x28, 0
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li x29, 0
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li x30, 0
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li x31, 0
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#endif
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# ===== Startup Stage 2 =====
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# Load code section from FLASH to RAM
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# when code LMA is different with VMA
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# test: using psram before loading
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#ifndef RS_SOC_TINY
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# Define the addresses
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.equ GPIO_ALT_ENABLE, RS_SOC_APB4_GPIO_ADMIN_BASE + 0x34
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.equ GPIO_ALT_SELECT, RS_SOC_APB4_GPIO_ADMIN_BASE + 0x38
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.equ BIT_MASK, 0x3FE00000 # Bits 21 to 29 set to 1
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.equ PSRAM_COMMAND, RS_SOC_APB4_PSRAM_BASE + 0x04
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.equ PSRAM_STATUS, RS_SOC_APB4_PSRAM_BASE + 0x08
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.equ PSRAM_INIT, 0x01
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.equ PSRAM_READY, 0x20
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PINMUX_PSRAM:
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li t0, GPIO_ALT_ENABLE
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lw t1, 0(t0)
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li t2, BIT_MASK
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or t1, t1, t2
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sw t1, 0(t0)
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li t0, GPIO_ALT_SELECT
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lw t1, 0(t0)
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or t1, t1, t2
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sw t1, 0(t0)
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PSRAM_INIT_TRG:
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li t0, PSRAM_COMMAND
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li t1, PSRAM_INIT
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sw t1, 0(t0)
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PSRAM_READY_WAIT:
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li t0, PSRAM_STATUS
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lw t1, 0(t0)
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andi t1, t1, PSRAM_READY
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beqz t1, PSRAM_READY_WAIT
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#endif
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app_loader_start:
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la a0, _ram_lma
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la a1, _ram_vma
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beq a0, a1, data_loader_start # flash xip
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la a2, _etext
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bgeu a1, a2, data_loader_start
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app_loader:
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lw t0, (a0)
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sw t0, (a1)
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addi a0, a0, 4
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addi a1, a1, 4
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bltu a1, a2, app_loader
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data_loader_start:
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la a0, _psram_lma
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la a1, _psram_vma
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beq a0, a1, bss_cleaner_start
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la a2, _edata
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bgeu a1, a2, bss_cleaner_start
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data_loader:
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lw t0, (a0)
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sw t0, (a1)
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addi a0, a0, 4
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addi a1, a1, 4
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bltu a1, a2, data_loader
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bss_cleaner_start:
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la a0, _sbss
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la a1, _ebss
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bge a0, a1, main_start
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bss_cleaner:
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sw zero, 0(a0)
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addi a0, a0, 4
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blt a0, a1, bss_cleaner
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main_start:
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# call main
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#ifdef CSR_ENABLE
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call _premain_init # init irq
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#endif
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call main
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loop:
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j loop
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