mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
- Introduced new Tiny Gen1 datasheet with waveform rendering capabilities. - Implemented example functions for various peripherals including archinfo, clint, dma, gpio, i2c, pwm, rtc, sram, sysctrl, timer, uart, wdg, and xpi. - Enhanced register reference parsing to accommodate Tiny-specific memory maps. - Created a dedicated Tiny reference module to isolate Tiny publications from Mini inputs. - Developed comprehensive tests to validate Tiny publication configurations, register inventories, and evidence claims. - Updated RTL documentation to reflect the separation of Tiny and Mini product lines.
218 lines
4.1 KiB
JSON
218 lines
4.1 KiB
JSON
{
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"schema_version": 1,
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"state": "frozen",
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"ip_ids": [
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"xpi",
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"sram",
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"gpio",
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"dma",
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"timer",
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"pwm",
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"rtc",
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"wdg",
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"uart0",
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"uart1",
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"i2c",
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"sysctrl",
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"clint",
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"archinfo"
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],
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"entries": [
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{
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"level": 1,
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"title": "Product Brief",
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"anchor": null
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},
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{
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"level": 2,
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"title": "Features",
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"anchor": null
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},
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{
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"level": 2,
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"title": "Configuration and Scope",
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"anchor": "tiny-configuration"
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},
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{
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"level": 2,
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"title": "Reading and Evidence Conventions",
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"anchor": null
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},
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{
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"level": 1,
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"title": "System Architecture",
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"anchor": null
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},
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{
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"level": 2,
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"title": "Processor and Integration",
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"anchor": "tiny-core"
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},
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{
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"level": 2,
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"title": "Clock, Reset and Operating State",
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"anchor": "tiny-clock"
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},
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{
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"level": 2,
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"title": "Bus Transactions, Arbitration and Errors",
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"anchor": "tiny-bus"
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},
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{
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"level": 2,
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"title": "Memory Map and Access Conventions",
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"anchor": "tiny-addresses"
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},
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{
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"level": 2,
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"title": "Interrupt and DMA Request Routing",
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"anchor": "tiny-irq"
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},
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{
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"level": 2,
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"title": "Peripherals",
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"anchor": null
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},
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{
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"level": 3,
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"title": "XPI Universal Controller",
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"anchor": "xpi"
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},
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{
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"level": 3,
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"title": "On-Chip SRAM",
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"anchor": "sram"
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},
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{
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"level": 3,
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"title": "General-Purpose Input/Output (GPIO)",
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"anchor": "gpio"
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},
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{
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"level": 3,
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"title": "Direct Memory Access (DMA)",
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"anchor": "dma"
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},
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{
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"level": 3,
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"title": "General-Purpose Timers (TIM0, TIM1)",
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"anchor": "timer"
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},
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{
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"level": 3,
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"title": "Pulse Width Modulation (PWM)",
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"anchor": "pwm"
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},
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{
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"level": 3,
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"title": "Real-Time Clock (RTC)",
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"anchor": "rtc"
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},
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{
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"level": 3,
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"title": "Watchdog (WDG)",
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"anchor": "wdg"
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},
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{
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"level": 3,
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"title": "Management UART (UART0)",
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"anchor": "uart0"
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},
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{
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"level": 3,
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"title": "Second UART (UART1)",
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"anchor": "uart1"
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},
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{
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"level": 3,
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"title": "Inter-Integrated Circuit (I2C0, I2C1)",
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"anchor": "i2c"
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},
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{
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"level": 3,
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"title": "System Controller (SYSCTRL)",
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"anchor": "sysctrl"
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},
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{
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"level": 3,
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"title": "Local Interrupt Controller (CLINT)",
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"anchor": "clint"
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},
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{
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"level": 3,
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"title": "Architecture Information (ARCHINFO)",
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"anchor": "archinfo"
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},
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{
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"level": 2,
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"title": "Pins and Board Connections",
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"anchor": "tiny-pins"
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},
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{
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"level": 2,
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"title": "Electrical, Package and Reliability Boundaries",
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"anchor": null
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},
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{
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"level": 1,
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"title": "Software",
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"anchor": null
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},
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{
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"level": 2,
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"title": "Reset, Boot and Linker Layout",
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"anchor": "tiny-boot"
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},
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{
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"level": 2,
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"title": "SDK, API Completion and Polling",
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"anchor": null
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},
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{
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"level": 2,
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"title": "DMA Descriptors and Buffer Lifetime",
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"anchor": "tiny-dma-format"
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},
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{
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"level": 2,
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"title": "Acceptance and Diagnostics",
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"anchor": "tiny-diagnostics"
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},
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{
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"level": 1,
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"title": "Implementation and Evidence",
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"anchor": null
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},
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{
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"level": 2,
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"title": "Reproducible Development Flow",
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"anchor": null
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},
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{
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"level": 2,
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"title": "Verification Status and Qualification Gaps",
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"anchor": "tiny-evidence"
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},
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{
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"level": 1,
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"title": "Appendix: Global Register Index",
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"anchor": "tiny-register-index"
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},
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{
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"level": 1,
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"title": "Document Control",
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"anchor": null
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},
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{
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"level": 2,
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"title": "Revision History",
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"anchor": null
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},
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{
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"level": 2,
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"title": "Sources, License and Contact",
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"anchor": "publication-provenance"
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}
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]
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}
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