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maksyuki c8187284d0 feat(tiny): add scripts for SDC generation and packaging

- Introduced  to create pad-aware timing constraints for the Tiny IHP130 chip flow.
- Added  to create a checksummed delivery archive for the Tiny LibreLane implementation.
- Created  for synthesis-only header of the locked IHP SRAM macro physical views.
- Implemented  to limit OpenSTA report enumeration for path counts.
- Updated  to include power pad definitions.
- Enhanced  to handle power pad counts and validation.
- Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.

2026-09-27 08:48:12 +08:00

comb.py

feat: refactor test scripts to update paths and improve organization

2026-09-25 15:44:02 +08:00

convt_sv2v.py

feat: refactor test scripts to update paths and improve organization

2026-09-25 15:44:02 +08:00

filelist_deps.py

feat: refactor test scripts to update paths and improve organization

2026-09-25 15:44:02 +08:00

filelist.py

feat: refactor test scripts to update paths and improve organization

2026-09-25 15:44:02 +08:00

generate_memory_map.py

feat: refactor test scripts to update paths and improve organization

2026-09-25 15:44:02 +08:00

generate_pin_map.py

feat(tiny): add scripts for SDC generation and packaging

2026-09-27 08:48:12 +08:00

prepare_norflash.py

feat: refactor test scripts to update paths and improve organization

2026-09-25 15:44:02 +08:00

README.md

feat: refactor test scripts to update paths and improve organization

2026-09-25 15:44:02 +08:00

README.md

Shared RTL Flow Helpers

These product-independent helpers parse filelists, convert SystemVerilog, generate address/pad artifacts, and prepare simulation inputs. Both products invoke them here directly, with Python imports through scripts.rtl. Product inputs stay under their owning rtl/<product> directory; outputs stay below build/.

Changes require focused generator tests, Ruff and Pytest, plus compilation of each affected product. generate_tiny.py owns Tiny-only integration bindings.