mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-05 06:32:37 +00:00
maksyuki
a8325ab6b7
- Introduced a new testbench for the SDIO wrapper () to validate APB interactions. - Updated to include IRQ handling for SDIO0 and SDIO1. - Enhanced to account for performance management of SDIO0 and SDIO1. - Modified memory map tests to include SDIO base addresses and performance wait offsets. - Updated pin mapping tests to include SDIO1 signals. - Created a comprehensive suite of SDIO tests () covering various functionalities including CRC, command engine, DMA, and standalone operations. - Added a new test for verifying SDIO register parity against the RTL definition. - Adjusted SOC topology tests to reflect the addition of SDIO in the IRQ and APB fabric.
658 lines
26 KiB
Systemverilog
658 lines
26 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of the Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`timescale 1ns / 1ps
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module sdio_data #(
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parameter int TimeoutWidth = 32
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) (
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input logic clk_i,
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input logic rst_n_i,
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input logic launch_tick_i,
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input logic sample_tick_i,
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input logic start_i,
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input logic abort_i,
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input sdio_pkg::sdio_data_direction_e direction_i,
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input logic [ 1:0] bus_width_i,
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input logic [ 15:0] block_size_i,
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input logic [ 15:0] block_count_i,
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input logic [TimeoutWidth-1:0] timeout_cycles_i,
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input logic [TimeoutWidth-1:0] busy_timeout_cycles_i,
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input logic [ 3:0] dat_di_i,
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input logic dat0_i,
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output logic [ 3:0] dat_oe_o,
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output logic [ 3:0] dat_do_o,
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input logic tx_valid_i,
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output logic tx_ready_o,
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output logic tx_wait_o,
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input logic [ 31:0] tx_data_i,
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input logic [ 3:0] tx_strb_i,
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input logic tx_last_i,
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output logic rx_valid_o,
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input logic rx_ready_i,
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output logic [ 31:0] rx_data_o,
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output logic [ 3:0] rx_strb_o,
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output logic rx_last_o,
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output logic busy_o,
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output logic done_o,
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output logic error_o,
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output logic timeout_o,
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output logic crc_error_o,
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output logic busy_timeout_o
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);
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typedef enum logic [3:0] {
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Idle,
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WriteWaitWord,
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WriteNextWord,
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WriteToken,
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WritePayload,
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WriteCrc,
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WriteResponse,
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WriteBusy,
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ReadToken,
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ReadPayload,
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ReadEmit,
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ReadCrc
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} data_state_e;
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data_state_e s_state_d, s_state_q;
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logic s_width4_d, s_width4_q;
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logic [31:0] s_target_bytes_d, s_target_bytes_q;
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logic [31:0] s_tx_total_d, s_tx_total_q;
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logic [31:0] s_rx_total_d, s_rx_total_q;
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logic [31:0] s_tx_word_d, s_tx_word_q;
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logic [3:0] s_tx_strb_d, s_tx_strb_q;
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logic [2:0] s_tx_active_bytes_d, s_tx_active_bytes_q;
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logic [2:0] s_tx_byte_d, s_tx_byte_q;
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logic [3:0] s_tx_bit_d, s_tx_bit_q;
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logic [15:0] s_tx_crc_d, s_tx_crc_q;
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logic [63:0] s_tx_crc_lanes_d, s_tx_crc_lanes_q;
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logic s_tx_token_launched_d, s_tx_token_launched_q;
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logic [4:0] s_crc_bit_d, s_crc_bit_q;
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logic s_tx_crc_final_hold_d, s_tx_crc_final_hold_q;
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logic [31:0] s_rx_word_d, s_rx_word_q;
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logic [7:0] s_rx_byte_d, s_rx_byte_q;
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logic [2:0] s_rx_active_bytes_d, s_rx_active_bytes_q;
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logic [2:0] s_rx_byte_didx_d, s_rx_byte_didx_q;
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logic [3:0] s_rx_bit_d, s_rx_bit_q;
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logic [15:0] s_rx_crc_d, s_rx_crc_q;
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logic [63:0] s_rx_crc_lanes_d, s_rx_crc_lanes_q;
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logic [15:0] s_rx_crc_received_d, s_rx_crc_received_q;
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logic [63:0] s_rx_crc_received_lanes_d, s_rx_crc_received_lanes_q;
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logic [31:0] s_rx_pending_data_d, s_rx_pending_data_q;
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logic [3:0] s_rx_pending_strb_d, s_rx_pending_strb_q;
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logic s_rx_pending_last_d, s_rx_pending_last_q;
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logic [4:0] s_resp_token_d, s_resp_token_q;
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logic [2:0] s_resp_bit_d, s_resp_bit_q;
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logic [TimeoutWidth-1:0] s_timeout_count_d, s_timeout_count_q;
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logic s_done_d, s_done_q;
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logic s_err_d, s_err_q;
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logic s_timeout_d, s_timeout_q;
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logic s_crc_err_d, s_crc_err_q;
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logic s_busy_timeout_d, s_busy_timeout_q;
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logic [ 31:0] s_target_bytes_calc;
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logic [ 7:0] s_rx_byte_next;
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logic [ 31:0] s_rx_remaining;
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logic [TimeoutWidth-1:0] s_phase_timeout;
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logic s_timeout_expired;
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logic s_tx_word_final;
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function automatic logic [2:0] count_strobe(input logic [3:0] strb_i);
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logic [2:0] count;
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begin
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count = 3'd0;
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for (int index = 0; index < 4; index++) begin
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if (strb_i[index]) begin
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count = count + 1'b1;
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end
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end
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return count;
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end
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endfunction
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function automatic logic strobe_valid(input logic [3:0] strb_i);
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return (strb_i != 4'd0) && ((strb_i & (strb_i + 4'd1)) == 4'd0);
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endfunction
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function automatic logic [63:0] update_lane_crc(
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input logic [63:0] crc_i, input logic [3:0] bits_i, input logic [2:0] lane_count_i);
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logic [63:0] crc;
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begin
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crc = crc_i;
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for (int lane = 0; lane < 4; lane++) begin
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if (lane < lane_count_i) begin
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crc[lane*16+:16] = sdio_pkg::sdio_crc16_next(crc_i[lane*16+:16], bits_i[lane]);
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end
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end
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return crc;
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end
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endfunction
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function automatic logic [3:0] tx_lane_bits(input logic [31:0] word_i, input logic [3:0] bit_i);
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logic [3:0] bits;
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begin
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bits = 4'b0000;
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for (int lane = 0; lane < 4; lane++) begin
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bits[lane] = word_i[lane*8+(int'(7)-int'(bit_i))];
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end
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return bits;
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end
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endfunction
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assign s_target_bytes_calc = {16'd0, block_size_i} * {16'd0, block_count_i};
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assign s_rx_remaining = s_target_bytes_q - s_rx_total_q;
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assign s_rx_byte_next = {s_rx_byte_q[6:0], dat_di_i[0]};
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assign s_phase_timeout = (s_state_q == WriteBusy) ? busy_timeout_cycles_i : timeout_cycles_i;
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assign s_timeout_expired = (s_phase_timeout == '0) || (s_timeout_count_q >= s_phase_timeout);
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assign s_tx_word_final = s_width4_q
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? (s_tx_bit_q == 4'd7)
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: ((s_tx_bit_q == 4'd7) &&
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(s_tx_byte_q + 1'b1 >= s_tx_active_bytes_q));
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assign tx_ready_o = (s_state_q == WriteWaitWord) || (s_state_q == WriteNextWord) ||
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((s_state_q == WritePayload) && launch_tick_i && s_tx_word_final &&
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(s_tx_total_q < s_target_bytes_q));
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assign tx_wait_o = (s_state_q == WriteWaitWord) || (s_state_q == WriteNextWord);
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assign rx_valid_o = (s_state_q == ReadEmit);
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assign rx_data_o = s_rx_pending_data_q;
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assign rx_strb_o = s_rx_pending_strb_q;
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assign rx_last_o = s_rx_pending_last_q;
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assign busy_o = s_state_q != Idle;
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assign done_o = s_done_q;
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assign error_o = s_err_q;
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assign timeout_o = s_timeout_q;
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assign crc_error_o = s_crc_err_q;
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assign busy_timeout_o = s_busy_timeout_q;
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`ifndef SYNTHESIS
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always_ff @(posedge clk_i) begin
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if (tx_valid_i && tx_ready_o && tx_last_i) begin
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assert (s_tx_total_q + {29'd0, count_strobe(tx_strb_i)} >= s_target_bytes_q)
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else $error("sdio_data: tx_last asserted before the target byte count");
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end
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end
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`endif
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always_comb begin
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dat_oe_o = 4'b0000;
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dat_do_o = 4'b1111;
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if ((s_state_q == WriteToken) || (s_state_q == WritePayload) ||
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(s_state_q == WriteCrc) || s_tx_crc_final_hold_q) begin
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if (s_width4_q) begin
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dat_oe_o = (s_tx_active_bytes_q >= 3'd4)
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? 4'b1111
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: ((4'b0001 << s_tx_active_bytes_q) - 1'b1);
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end else begin
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dat_oe_o = 4'b0001;
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end
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end
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if (s_state_q == WriteToken) begin
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dat_do_o = 4'b0000;
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end else if ((s_state_q == WritePayload) && s_width4_q) begin
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dat_do_o = 4'b1111;
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for (int lane = 0; lane < 4; lane++) begin
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if (lane < s_tx_active_bytes_q) begin
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dat_do_o[lane] = s_tx_word_q[lane*8+(int'(7)-int'(s_tx_bit_q))];
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end
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end
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end else if (s_state_q == WritePayload) begin
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dat_do_o[0] = s_tx_word_q[s_tx_byte_q*8+(int'(7)-int'(s_tx_bit_q))];
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end else if ((s_state_q == WriteCrc) || s_tx_crc_final_hold_q) begin
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if (s_width4_q) begin
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dat_do_o = 4'b1111;
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for (int lane = 0; lane < 4; lane++) begin
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if (lane < s_tx_active_bytes_q) begin
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dat_do_o[lane] = s_tx_crc_lanes_q[lane*16+(int'(15)-int'(s_crc_bit_q))];
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end
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end
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end else begin
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dat_do_o[0] = s_tx_crc_q[int'(15)-int'(s_crc_bit_q)];
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end
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end
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end
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always_comb begin
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s_state_d = s_state_q;
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s_width4_d = s_width4_q;
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s_target_bytes_d = s_target_bytes_q;
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s_tx_total_d = s_tx_total_q;
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s_rx_total_d = s_rx_total_q;
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s_tx_word_d = s_tx_word_q;
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s_tx_strb_d = s_tx_strb_q;
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s_tx_active_bytes_d = s_tx_active_bytes_q;
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s_tx_byte_d = s_tx_byte_q;
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s_tx_bit_d = s_tx_bit_q;
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s_tx_crc_d = s_tx_crc_q;
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s_tx_crc_lanes_d = s_tx_crc_lanes_q;
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s_tx_token_launched_d = s_tx_token_launched_q;
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s_crc_bit_d = s_crc_bit_q;
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s_tx_crc_final_hold_d = s_tx_crc_final_hold_q;
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s_rx_word_d = s_rx_word_q;
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s_rx_byte_d = s_rx_byte_q;
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s_rx_active_bytes_d = s_rx_active_bytes_q;
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s_rx_byte_didx_d = s_rx_byte_didx_q;
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s_rx_bit_d = s_rx_bit_q;
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s_rx_crc_d = s_rx_crc_q;
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s_rx_crc_lanes_d = s_rx_crc_lanes_q;
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s_rx_crc_received_d = s_rx_crc_received_q;
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s_rx_crc_received_lanes_d = s_rx_crc_received_lanes_q;
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s_rx_pending_data_d = s_rx_pending_data_q;
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s_rx_pending_strb_d = s_rx_pending_strb_q;
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s_rx_pending_last_d = s_rx_pending_last_q;
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s_resp_token_d = s_resp_token_q;
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s_resp_bit_d = s_resp_bit_q;
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s_timeout_count_d = s_timeout_count_q;
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s_done_d = 1'b0;
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s_err_d = s_err_q;
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s_timeout_d = s_timeout_q;
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s_crc_err_d = s_crc_err_q;
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s_busy_timeout_d = s_busy_timeout_q;
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if (s_tx_crc_final_hold_q && sample_tick_i) begin
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s_tx_crc_final_hold_d = 1'b0;
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end
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if ((s_state_q != Idle) && s_timeout_expired) begin
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s_state_d = Idle;
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s_done_d = 1'b1;
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s_err_d = 1'b1;
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s_timeout_d = 1'b1;
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s_busy_timeout_d = (s_state_q == WriteBusy);
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s_tx_crc_final_hold_d = 1'b0;
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end else if (s_state_q != Idle) begin
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s_timeout_count_d = s_timeout_count_q + 1'b1;
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end
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if (abort_i && (s_state_q != Idle)) begin
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s_state_d = Idle;
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s_done_d = 1'b1;
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s_err_d = 1'b1;
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s_tx_crc_final_hold_d = 1'b0;
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end else if (s_state_q == Idle) begin
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if (start_i) begin
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s_width4_d = bus_width_i == 2'd1;
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s_target_bytes_d = s_target_bytes_calc;
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s_tx_total_d = '0;
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s_rx_total_d = '0;
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s_tx_word_d = '0;
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s_tx_strb_d = '0;
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s_tx_active_bytes_d = '0;
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s_tx_byte_d = '0;
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s_tx_bit_d = '0;
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s_tx_crc_d = '0;
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s_tx_crc_lanes_d = '0;
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s_tx_token_launched_d = 1'b0;
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s_crc_bit_d = '0;
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s_tx_crc_final_hold_d = 1'b0;
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s_rx_word_d = '0;
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s_rx_byte_d = '0;
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s_rx_active_bytes_d = (s_target_bytes_calc >= 32'd4) ? 3'd4 : s_target_bytes_calc[2:0];
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s_rx_byte_didx_d = '0;
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s_rx_bit_d = '0;
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s_rx_crc_d = '0;
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s_rx_crc_lanes_d = '0;
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s_rx_crc_received_d = '0;
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s_rx_crc_received_lanes_d = '0;
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s_rx_pending_data_d = '0;
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s_rx_pending_strb_d = '0;
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s_rx_pending_last_d = 1'b0;
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s_resp_token_d = '0;
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s_resp_bit_d = '0;
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s_timeout_count_d = '0;
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s_err_d = s_target_bytes_calc == 32'd0;
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s_timeout_d = 1'b0;
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s_crc_err_d = 1'b0;
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s_busy_timeout_d = 1'b0;
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if (s_target_bytes_calc == 32'd0) begin
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s_state_d = Idle;
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s_done_d = 1'b1;
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end else if (direction_i == sdio_pkg::SdioDataToCard) begin
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s_state_d = WriteWaitWord;
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end else begin
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s_state_d = ReadToken;
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end
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end
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end else begin
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unique case (s_state_q)
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WriteWaitWord, WriteNextWord: begin
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if (tx_valid_i && tx_ready_o) begin
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s_tx_active_bytes_d = count_strobe(tx_strb_i);
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s_tx_word_d = tx_data_i;
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s_tx_strb_d = tx_strb_i;
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s_tx_byte_d = '0;
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s_tx_bit_d = '0;
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if (s_state_q == WriteWaitWord) begin
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s_tx_crc_d = '0;
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s_tx_crc_lanes_d = '0;
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end
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s_tx_token_launched_d = 1'b0;
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s_tx_total_d = s_tx_total_q + {29'd0, count_strobe(tx_strb_i)};
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s_tx_crc_final_hold_d = 1'b0;
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s_timeout_count_d = '0;
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if (!strobe_valid(
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tx_strb_i
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) || (s_tx_total_q + {29'd0, count_strobe(
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tx_strb_i
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)} > s_target_bytes_q)) begin
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s_state_d = Idle;
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s_done_d = 1'b1;
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s_err_d = 1'b1;
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end else begin
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s_state_d = (s_state_q == WriteWaitWord) ? WriteToken : WritePayload;
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end
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end
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end
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WriteToken: begin
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if (sample_tick_i) begin
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s_tx_token_launched_d = 1'b1;
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end
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if (launch_tick_i && s_tx_token_launched_q) begin
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s_state_d = WritePayload;
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s_tx_byte_d = '0;
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s_tx_bit_d = '0;
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s_timeout_count_d = '0;
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s_tx_token_launched_d = 1'b0;
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end
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end
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WritePayload: begin
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if (launch_tick_i) begin
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if (s_width4_q) begin
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s_tx_crc_lanes_d = update_lane_crc(
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s_tx_crc_lanes_q, tx_lane_bits(s_tx_word_q, s_tx_bit_q), s_tx_active_bytes_q);
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if (s_tx_bit_q == 4'd7) begin
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if (s_tx_total_q >= s_target_bytes_q) begin
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s_state_d = WriteCrc;
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s_crc_bit_d = '0;
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end else if (tx_valid_i && tx_ready_o) begin
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s_tx_word_d = tx_data_i;
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s_tx_strb_d = tx_strb_i;
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s_tx_active_bytes_d = count_strobe(tx_strb_i);
|
|
s_tx_total_d = s_tx_total_q + {29'd0, count_strobe(tx_strb_i)};
|
|
s_tx_byte_d = '0;
|
|
s_tx_bit_d = '0;
|
|
end else begin
|
|
s_state_d = WriteNextWord;
|
|
end
|
|
end else begin
|
|
s_tx_bit_d = s_tx_bit_q + 1'b1;
|
|
end
|
|
end else if (s_tx_bit_q == 4'd7) begin
|
|
s_tx_crc_d = sdio_pkg::sdio_crc16_byte(s_tx_crc_q, s_tx_word_q[s_tx_byte_q*8+:8]);
|
|
if (s_tx_byte_q + 1'b1 >= s_tx_active_bytes_q) begin
|
|
if (s_tx_total_q >= s_target_bytes_q) begin
|
|
s_state_d = WriteCrc;
|
|
s_crc_bit_d = '0;
|
|
end else if (tx_valid_i && tx_ready_o) begin
|
|
s_tx_word_d = tx_data_i;
|
|
s_tx_strb_d = tx_strb_i;
|
|
s_tx_active_bytes_d = count_strobe(tx_strb_i);
|
|
s_tx_total_d = s_tx_total_q + {29'd0, count_strobe(tx_strb_i)};
|
|
s_tx_byte_d = '0;
|
|
s_tx_bit_d = '0;
|
|
end else begin
|
|
s_state_d = WriteNextWord;
|
|
end
|
|
end else begin
|
|
s_tx_byte_d = s_tx_byte_q + 1'b1;
|
|
s_tx_bit_d = '0;
|
|
end
|
|
end else begin
|
|
s_tx_bit_d = s_tx_bit_q + 1'b1;
|
|
end
|
|
end
|
|
end
|
|
WriteCrc: begin
|
|
if (launch_tick_i) begin
|
|
if (s_crc_bit_q == 5'd15) begin
|
|
s_tx_crc_final_hold_d = 1'b1;
|
|
s_state_d = WriteResponse;
|
|
s_resp_token_d = '0;
|
|
s_resp_bit_d = '0;
|
|
s_timeout_count_d = '0;
|
|
end else begin
|
|
s_crc_bit_d = s_crc_bit_q + 1'b1;
|
|
end
|
|
end
|
|
end
|
|
WriteResponse: begin
|
|
if (launch_tick_i && !s_tx_crc_final_hold_q) begin
|
|
s_resp_token_d = {s_resp_token_q[3:0], dat0_i};
|
|
if (s_resp_bit_q == 3'd4) begin
|
|
if ({s_resp_token_q[3:0], dat0_i} == 5'b00101) begin
|
|
s_state_d = WriteBusy;
|
|
s_timeout_count_d = '0;
|
|
end else begin
|
|
s_state_d = Idle;
|
|
s_done_d = 1'b1;
|
|
s_err_d = 1'b1;
|
|
if ({s_resp_token_q[3:0], dat0_i} == 5'b01011) begin
|
|
s_crc_err_d = 1'b1;
|
|
end
|
|
end
|
|
end else begin
|
|
s_resp_bit_d = s_resp_bit_q + 1'b1;
|
|
end
|
|
end
|
|
end
|
|
WriteBusy: begin
|
|
if (sample_tick_i && dat0_i) begin
|
|
if (s_tx_total_q >= s_target_bytes_q) begin
|
|
s_state_d = Idle;
|
|
s_done_d = 1'b1;
|
|
end else begin
|
|
s_state_d = WriteWaitWord;
|
|
s_timeout_count_d = '0;
|
|
end
|
|
end
|
|
end
|
|
ReadToken: begin
|
|
if (sample_tick_i && (dat_di_i == 4'b0000)) begin
|
|
s_state_d = ReadPayload;
|
|
s_rx_word_d = '0;
|
|
s_rx_byte_d = '0;
|
|
s_rx_byte_didx_d = '0;
|
|
s_rx_bit_d = '0;
|
|
s_rx_crc_d = '0;
|
|
s_rx_crc_lanes_d = '0;
|
|
s_timeout_count_d = '0;
|
|
end
|
|
end
|
|
ReadPayload: begin
|
|
if (sample_tick_i) begin
|
|
if (s_width4_q) begin
|
|
for (int lane = 0; lane < 4; lane++) begin
|
|
if (lane < s_rx_active_bytes_q) begin
|
|
s_rx_word_d[lane*8+(int'(7)-int'(s_rx_bit_q))] = dat_di_i[lane];
|
|
s_rx_crc_lanes_d[lane*16+:16] =
|
|
sdio_pkg::sdio_crc16_next(s_rx_crc_lanes_q[lane*16+:16], dat_di_i[lane]);
|
|
end
|
|
end
|
|
if (s_rx_bit_q == 4'd7) begin
|
|
s_rx_pending_data_d = s_rx_word_d;
|
|
s_rx_pending_strb_d = (4'b0001 << s_rx_active_bytes_q) - 1'b1;
|
|
s_rx_pending_last_d =
|
|
s_rx_total_q + {29'd0, s_rx_active_bytes_q} >= s_target_bytes_q;
|
|
s_rx_total_d = s_rx_total_q + {29'd0, s_rx_active_bytes_q};
|
|
s_state_d = ReadEmit;
|
|
end else begin
|
|
s_rx_bit_d = s_rx_bit_q + 1'b1;
|
|
end
|
|
end else begin
|
|
s_rx_byte_d = s_rx_byte_next;
|
|
if (s_rx_bit_q == 4'd7) begin
|
|
s_rx_word_d[s_rx_byte_didx_q*8+:8] = s_rx_byte_next;
|
|
s_rx_byte_d = '0;
|
|
if (s_rx_byte_didx_q + 1'b1 >= s_rx_active_bytes_q) begin
|
|
s_rx_pending_data_d = s_rx_word_d;
|
|
s_rx_pending_strb_d = (4'b0001 << s_rx_active_bytes_q) - 1'b1;
|
|
s_rx_pending_last_d =
|
|
s_rx_total_q + {29'd0, s_rx_active_bytes_q} >= s_target_bytes_q;
|
|
s_rx_total_d = s_rx_total_q + {29'd0, s_rx_active_bytes_q};
|
|
s_state_d = ReadEmit;
|
|
end else begin
|
|
s_rx_byte_didx_d = s_rx_byte_didx_q + 1'b1;
|
|
s_rx_bit_d = '0;
|
|
end
|
|
s_rx_crc_d = sdio_pkg::sdio_crc16_byte(s_rx_crc_q, s_rx_byte_next);
|
|
end else begin
|
|
s_rx_bit_d = s_rx_bit_q + 1'b1;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
ReadEmit: begin
|
|
if (rx_valid_o && rx_ready_i) begin
|
|
if (s_rx_pending_last_q) begin
|
|
s_crc_bit_d = '0;
|
|
s_state_d = ReadCrc;
|
|
end else begin
|
|
s_rx_word_d = '0;
|
|
s_rx_byte_d = '0;
|
|
s_rx_active_bytes_d = (s_rx_remaining >= 32'd4) ? 3'd4 : s_rx_remaining[2:0];
|
|
s_rx_byte_didx_d = '0;
|
|
s_rx_bit_d = '0;
|
|
s_state_d = ReadPayload;
|
|
s_timeout_count_d = '0;
|
|
end
|
|
end
|
|
end
|
|
ReadCrc: begin
|
|
if (sample_tick_i) begin
|
|
if (s_width4_q) begin
|
|
for (int lane = 0; lane < 4; lane++) begin
|
|
if (lane < s_rx_active_bytes_q) begin
|
|
s_rx_crc_received_lanes_d[lane*16+:16] = {
|
|
s_rx_crc_received_lanes_q[lane*16+14-:15], dat_di_i[lane]
|
|
};
|
|
end
|
|
end
|
|
if (s_crc_bit_q == 5'd15) begin
|
|
for (int lane = 0; lane < 4; lane++) begin
|
|
if ((lane < s_rx_active_bytes_q) &&
|
|
(s_rx_crc_received_lanes_d[lane*16+:16] !=
|
|
s_rx_crc_lanes_q[lane*16+:16])) begin
|
|
s_err_d = 1'b1;
|
|
s_crc_err_d = 1'b1;
|
|
end
|
|
end
|
|
s_state_d = Idle;
|
|
s_done_d = 1'b1;
|
|
end else begin
|
|
s_crc_bit_d = s_crc_bit_q + 1'b1;
|
|
end
|
|
end else begin
|
|
s_rx_crc_received_d = {s_rx_crc_received_q[14:0], dat_di_i[0]};
|
|
if (s_crc_bit_q == 5'd15) begin
|
|
if ({s_rx_crc_received_q[14:0], dat_di_i[0]} != s_rx_crc_q) begin
|
|
s_err_d = 1'b1;
|
|
s_crc_err_d = 1'b1;
|
|
end
|
|
s_state_d = Idle;
|
|
s_done_d = 1'b1;
|
|
end else begin
|
|
s_crc_bit_d = s_crc_bit_q + 1'b1;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
default: begin
|
|
s_state_d = Idle;
|
|
s_err_d = 1'b1;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
always_ff @(posedge clk_i or negedge rst_n_i) begin
|
|
if (!rst_n_i) begin
|
|
s_state_q <= Idle;
|
|
s_width4_q <= 1'b0;
|
|
s_target_bytes_q <= '0;
|
|
s_tx_total_q <= '0;
|
|
s_rx_total_q <= '0;
|
|
s_tx_word_q <= '0;
|
|
s_tx_strb_q <= '0;
|
|
s_tx_active_bytes_q <= '0;
|
|
s_tx_byte_q <= '0;
|
|
s_tx_bit_q <= '0;
|
|
s_tx_crc_q <= '0;
|
|
s_tx_crc_lanes_q <= '0;
|
|
s_tx_token_launched_q <= 1'b0;
|
|
s_crc_bit_q <= '0;
|
|
s_tx_crc_final_hold_q <= 1'b0;
|
|
s_rx_word_q <= '0;
|
|
s_rx_byte_q <= '0;
|
|
s_rx_active_bytes_q <= '0;
|
|
s_rx_byte_didx_q <= '0;
|
|
s_rx_bit_q <= '0;
|
|
s_rx_crc_q <= '0;
|
|
s_rx_crc_lanes_q <= '0;
|
|
s_rx_crc_received_q <= '0;
|
|
s_rx_crc_received_lanes_q <= '0;
|
|
s_rx_pending_data_q <= '0;
|
|
s_rx_pending_strb_q <= '0;
|
|
s_rx_pending_last_q <= 1'b0;
|
|
s_resp_token_q <= '0;
|
|
s_resp_bit_q <= '0;
|
|
s_timeout_count_q <= '0;
|
|
s_done_q <= 1'b0;
|
|
s_err_q <= 1'b0;
|
|
s_timeout_q <= 1'b0;
|
|
s_crc_err_q <= 1'b0;
|
|
s_busy_timeout_q <= 1'b0;
|
|
end else begin
|
|
s_state_q <= s_state_d;
|
|
s_width4_q <= s_width4_d;
|
|
s_target_bytes_q <= s_target_bytes_d;
|
|
s_tx_total_q <= s_tx_total_d;
|
|
s_rx_total_q <= s_rx_total_d;
|
|
s_tx_word_q <= s_tx_word_d;
|
|
s_tx_strb_q <= s_tx_strb_d;
|
|
s_tx_active_bytes_q <= s_tx_active_bytes_d;
|
|
s_tx_byte_q <= s_tx_byte_d;
|
|
s_tx_bit_q <= s_tx_bit_d;
|
|
s_tx_crc_q <= s_tx_crc_d;
|
|
s_tx_crc_lanes_q <= s_tx_crc_lanes_d;
|
|
s_tx_token_launched_q <= s_tx_token_launched_d;
|
|
s_crc_bit_q <= s_crc_bit_d;
|
|
s_tx_crc_final_hold_q <= s_tx_crc_final_hold_d;
|
|
s_rx_word_q <= s_rx_word_d;
|
|
s_rx_byte_q <= s_rx_byte_d;
|
|
s_rx_active_bytes_q <= s_rx_active_bytes_d;
|
|
s_rx_byte_didx_q <= s_rx_byte_didx_d;
|
|
s_rx_bit_q <= s_rx_bit_d;
|
|
s_rx_crc_q <= s_rx_crc_d;
|
|
s_rx_crc_lanes_q <= s_rx_crc_lanes_d;
|
|
s_rx_crc_received_q <= s_rx_crc_received_d;
|
|
s_rx_crc_received_lanes_q <= s_rx_crc_received_lanes_d;
|
|
s_rx_pending_data_q <= s_rx_pending_data_d;
|
|
s_rx_pending_strb_q <= s_rx_pending_strb_d;
|
|
s_rx_pending_last_q <= s_rx_pending_last_d;
|
|
s_resp_token_q <= s_resp_token_d;
|
|
s_resp_bit_q <= s_resp_bit_d;
|
|
s_timeout_count_q <= s_timeout_count_d;
|
|
s_done_q <= s_done_d;
|
|
s_err_q <= s_err_d;
|
|
s_timeout_q <= s_timeout_d;
|
|
s_crc_err_q <= s_crc_err_d;
|
|
s_busy_timeout_q <= s_busy_timeout_d;
|
|
end
|
|
end
|
|
|
|
`ifndef SYNTHESIS
|
|
initial begin
|
|
if (TimeoutWidth < 1) begin
|
|
$fatal(1, "sdio_data: TimeoutWidth must be positive");
|
|
end
|
|
end
|
|
`endif
|
|
endmodule
|