mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
a8325ab6b7
- Introduced a new testbench for the SDIO wrapper () to validate APB interactions. - Updated to include IRQ handling for SDIO0 and SDIO1. - Enhanced to account for performance management of SDIO0 and SDIO1. - Modified memory map tests to include SDIO base addresses and performance wait offsets. - Updated pin mapping tests to include SDIO1 signals. - Created a comprehensive suite of SDIO tests () covering various functionalities including CRC, command engine, DMA, and standalone operations. - Added a new test for verifying SDIO register parity against the RTL definition. - Adjusted SOC topology tests to reflect the addition of SDIO in the IRQ and APB fabric.
291 lines
17 KiB
Makefile
291 lines
17 KiB
Makefile
FORMAL_DIR := $(VARIANT_ROOT)/formal
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FORMAL_SBY ?= sby
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FORMAL_BITWUZLA ?= $(shell command -v bitwuzla)
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FORMAL_SOLVER := bitwuzla
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FORMAL_SOLVER_DIR := $(FORMAL_DIR)/bin
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FORMAL_SOLVER_WRAPPER := $(FORMAL_SOLVER_DIR)/bitwuzla
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FORMAL_DEPTH ?= 20
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FORMAL_WS2812_DEPTH ?= 120
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FORMAL_I2C_DEPTH ?= 80
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FORMAL_CLINT_DEPTH ?= 32
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FORMAL_PSRAM_DEPTH ?= 32
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FORMAL_OPIPSRAM_DEPTH ?= 40
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FORMAL_OPIPSRAM_BMC_DEPTH ?= 40
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FORMAL_DMA_DEPTH ?= 24
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FORMAL_DMA_COVER_DEPTH ?= 32
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FORMAL_SDIO_DEPTH ?= 20
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FORMAL_SDIO_COVER_DEPTH ?= 24
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FORMAL_TIMEOUT ?= 60
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FORMAL_WS2812_TIMEOUT ?= 120
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FORMAL_I2C_TIMEOUT ?= 300
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FORMAL_OPIPSRAM_TIMEOUT ?= 300
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FORMAL_DMA_TIMEOUT ?= 120
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FORMAL_SDIO_TIMEOUT ?= 120
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FORMAL_TARGETS := bus rib_adapter rib2apb sysctrl pll_rcu gpio ws2812 uart i2c timer clint dvp i2s psram opipsram dma sdio
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FORMAL_FILELIST_GENERATOR := $(RTL_PATH)/formal/generate_formal_filelist.py
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FORMAL_SBY_GENERATOR := $(RTL_PATH)/formal/generate_sby_config.py
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FORMAL_RESULT_GENERATOR := $(RTL_PATH)/formal/formal_results.py
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FORMAL_SOURCE_FILES := $(RTL_PATH)/formal/bus_formal.sv \
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$(RTL_PATH)/formal/bus_formal_props.sv \
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$(RTL_PATH)/formal/rib_adapter_formal.sv \
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$(RTL_PATH)/formal/rib_adapter_formal_props.sv \
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$(RTL_PATH)/formal/rib2apb_formal.sv \
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$(RTL_PATH)/formal/rib2apb_formal_props.sv \
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$(RTL_PATH)/formal/sysctrl_formal.sv \
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$(RTL_PATH)/formal/sysctrl_formal_props.sv \
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$(RTL_PATH)/formal/pll_rcu_formal.sv \
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$(RTL_PATH)/formal/pll_rcu_formal_props.sv \
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$(RTL_PATH)/formal/gpio_formal.sv \
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$(RTL_PATH)/formal/gpio_formal_props.sv \
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$(RTL_PATH)/formal/ws2812_formal.sv \
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$(RTL_PATH)/formal/ws2812_formal_props.sv \
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$(RTL_PATH)/formal/uart_formal.sv \
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$(RTL_PATH)/formal/uart_formal_props.sv \
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$(RTL_PATH)/formal/i2c_formal.sv \
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$(RTL_PATH)/formal/i2c_formal_props.sv \
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$(RTL_PATH)/formal/timer_formal.sv \
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$(RTL_PATH)/formal/timer_formal_props.sv \
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$(RTL_PATH)/formal/clint_formal.sv \
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$(RTL_PATH)/formal/clint_formal_props.sv \
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$(RTL_PATH)/formal/dvp_formal.sv \
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$(RTL_PATH)/formal/dvp_formal_props.sv \
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$(RTL_PATH)/formal/i2s_formal.sv \
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$(RTL_PATH)/formal/i2s_formal_props.sv \
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$(RTL_PATH)/formal/psram_formal.sv \
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$(RTL_PATH)/formal/psram_formal_props.sv \
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$(RTL_PATH)/formal/opipsram_formal.sv \
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$(RTL_PATH)/formal/opipsram_formal_props.sv \
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$(RTL_PATH)/formal/dma_formal.sv \
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$(RTL_PATH)/formal/dma_formal_props.sv \
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$(RTL_PATH)/formal/sdio_formal.sv \
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$(RTL_PATH)/formal/sdio_formal_props.sv \
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$(RTL_PATH)/top/rib_bus.sv \
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$(RTL_PATH)/top/rib_error_slave.sv \
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$(RTL_PATH)/top/rib_if.sv \
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$(RTL_PATH)/top/rib2ram.sv \
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$(RTL_PATH)/top/rib2ribp.sv \
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$(RTL_PATH)/top/rib2apb.sv \
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$(RTL_PATH)/top/ribp2rib.sv \
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$(ROOT_PATH)/rtl/ip/interconnect/ribp_regslice.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/gpio_if.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/user_gpio_if.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/gpio_core.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/gpio_reg.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/apb4_gpio.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/pll_ctrl_if.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/sysctrl_if.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/sysctrl_define.svh \
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$(ROOT_PATH)/rtl/ip/peripheral/sysctrl_reg.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/sysctrl_core.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/apb4_sysctrl.sv \
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$(ROOT_PATH)/rtl/ip/serial/ws2812_if.sv \
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$(ROOT_PATH)/rtl/ip/serial/ws2812_reg.sv \
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$(ROOT_PATH)/rtl/ip/serial/ws2812_core.sv \
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$(ROOT_PATH)/rtl/ip/serial/apb4_ws2812.sv \
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$(ROOT_PATH)/rtl/ip/serial/uart_if.sv \
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$(ROOT_PATH)/rtl/ip/serial/uart_baudgen.sv \
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$(ROOT_PATH)/rtl/ip/serial/apb4_uart_tx.sv \
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$(ROOT_PATH)/rtl/ip/serial/apb4_uart_rx.sv \
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$(ROOT_PATH)/rtl/ip/serial/uart_flow_ctrl.sv \
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$(ROOT_PATH)/rtl/ip/serial/uart_core.sv \
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$(ROOT_PATH)/rtl/ip/serial/uart_reg.sv \
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$(ROOT_PATH)/rtl/ip/serial/apb4_uart.sv \
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$(ROOT_PATH)/rtl/ip/serial/i2c_filter.sv \
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$(ROOT_PATH)/rtl/ip/serial/i2c_core.sv \
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$(ROOT_PATH)/rtl/ip/serial/i2c_reg.sv \
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$(ROOT_PATH)/rtl/ip/serial/apb4_i2c.sv \
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$(ROOT_PATH)/rtl/ip/serial/i2s_define.svh \
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$(ROOT_PATH)/rtl/ip/serial/i2s_pkg.sv \
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$(ROOT_PATH)/rtl/ip/serial/i2s_reg.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/i2c/rtl/i2c_if.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/timer_core.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/timer_define.svh \
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$(ROOT_PATH)/rtl/ip/peripheral/timer_reg.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/apb4_timer.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/clint_define.svh \
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$(ROOT_PATH)/rtl/ip/peripheral/clint_if.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/clint_reg.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/clint_core.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/apb4_clint.sv \
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$(ROOT_PATH)/rtl/ip/multimedia/dvp_define.svh \
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$(ROOT_PATH)/rtl/ip/multimedia/dvp_core.sv \
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$(ROOT_PATH)/rtl/ip/multimedia/dvp_reg.sv \
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$(ROOT_PATH)/rtl/ip/multimedia/axi4s_dvp.sv \
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$(ROOT_PATH)/rtl/ip/memory/psram_pkg.sv \
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$(ROOT_PATH)/rtl/ip/memory/psram_axi4.sv \
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$(ROOT_PATH)/rtl/ip/memory/psram_phy.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/utils/register.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/utils/xchecker.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/utils/gray2bin.sv \
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$(ROOT_PATH)/rtl/ip/util/async_fifo.sv \
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$(ROOT_PATH)/rtl/tech/tc_clk.sv \
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$(ROOT_PATH)/rtl/tech/tc_opipsram_delay.sv \
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$(ROOT_PATH)/rtl/ip/memory/opipsram_define.svh \
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$(ROOT_PATH)/rtl/ip/memory/opipsram_pkg.sv \
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$(ROOT_PATH)/rtl/ip/memory/opipsram_protocol.sv \
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$(ROOT_PATH)/rtl/ip/memory/opipsram_trx.sv \
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$(ROOT_PATH)/rtl/ip/memory/opipsram_axi4.sv \
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$(ROOT_PATH)/rtl/ip/memory/opipsram_core.sv \
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$(ROOT_PATH)/rtl/ip/memory/opipsram_phy.sv \
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$(ROOT_PATH)/rtl/ip/memory/opipsram_reg.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/dma_pkg.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/dma_req_if.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/dma_axi4_master.sv \
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$(ROOT_PATH)/rtl/ip/peripheral/dma_core.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/clkrst/counter.sv \
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$(RTL_PATH)/top/rcu.sv \
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$(RTL_PATH)/top/pll_rcu_controller.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/interface/apb4_if.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/interface/ribp_if.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/interface/apb4_pure_if.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/interface/axi4_if.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/interface/axi4_stream_if.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/cdc/cdc_rst_ctrlr.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/clkrst/rst_sync.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/utils/edge_det.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/utils/spill_register.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/utils/fifo.sv \
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$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/stream/round_robin_arbiter.sv \
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$(ROOT_PATH)/scripts/bitwuzla_smt2.py
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FORMAL_STAMPS := $(addsuffix /.stamp,$(addprefix $(FORMAL_DIR)/,$(FORMAL_TARGETS)))
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FORMAL_INTERMEDIATES := $(foreach target,$(FORMAL_TARGETS), \
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$(FORMAL_DIR)/$(target)/formal.fl $(FORMAL_DIR)/$(target)/design.v \
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$(FORMAL_DIR)/$(target)/prove.sby $(FORMAL_DIR)/$(target)/cover.sby \
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$(FORMAL_DIR)/$(target)/prove.stamp \
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$(FORMAL_DIR)/$(target)/cover.stamp) \
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$(FORMAL_DIR)/opipsram/bmc.sby $(FORMAL_DIR)/opipsram/bmc.stamp \
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$(FORMAL_SOLVER_WRAPPER)
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FORMAL_RESULT := $(META_DIR)/formal.json
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.SECONDARY: $(FORMAL_INTERMEDIATES)
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$(FORMAL_DIR)/%/formal.fl: $(FORMAL_FILELIST_GENERATOR) $(FORMAL_SOURCE_FILES) \
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$(MEMORY_MAP_STAMP) $(SOC_TOPOLOGY_STAMP) $(USER_EXTENSIONS_STAMP)
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@mkdir -p $(@D)
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python3 $(FORMAL_FILELIST_GENERATOR) --target $* --output $@ \
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--memory-map-dir $(MEMORY_MAP_DIR) --soc-topology-dir $(SOC_TOPOLOGY_DIR) \
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--user-extensions-dir $(USER_EXTENSIONS_DIR)
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$(FORMAL_DIR)/%/design.v: $(FORMAL_DIR)/%/formal.fl $(RTL_PATH)/script/convt_sv2v.py \
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$(RTL_PATH)/script/filelist.py
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool formal-sv2v \
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--log $(@D)/sv2v.log --result $(@D)/result-sv2v.json \
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-- python3 $(RTL_PATH)/script/convt_sv2v.py -f $< --output $@
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$(FORMAL_DIR)/%/prove.sby: $(FORMAL_DIR)/%/design.v $(RTL_PATH)/formal/%_formal_props.sv \
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$(FORMAL_SBY_GENERATOR)
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python3 $(FORMAL_SBY_GENERATOR) --top $*_formal --input $< \
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--properties $(RTL_PATH)/formal/$*_formal_props.sv --solver $(FORMAL_SOLVER) \
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--mode $(if $(filter dma sdio,$*),bmc,prove) --depth $(if $(filter dma,$*),$(FORMAL_DMA_DEPTH),$(if $(filter sdio,$*),$(FORMAL_SDIO_DEPTH),$(if $(filter opipsram,$*),$(FORMAL_OPIPSRAM_DEPTH),$(if $(filter ws2812,$*),$(FORMAL_WS2812_DEPTH),$(if $(filter i2c,$*),$(FORMAL_I2C_DEPTH),$(if $(filter clint,$*),$(FORMAL_CLINT_DEPTH),$(if $(filter psram,$*),$(FORMAL_PSRAM_DEPTH),$(FORMAL_DEPTH)))))))) --output $@
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@if [ "$*" = opipsram ]; then sed -i '/^async2sync/i clk2fflogic' $@; fi
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$(FORMAL_DIR)/%/cover.sby: $(FORMAL_DIR)/%/design.v $(RTL_PATH)/formal/%_formal_props.sv \
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$(FORMAL_SBY_GENERATOR)
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python3 $(FORMAL_SBY_GENERATOR) --top $*_formal --input $< \
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--properties $(RTL_PATH)/formal/$*_formal_props.sv --solver $(FORMAL_SOLVER) \
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--mode cover --depth $(if $(filter dma,$*),$(FORMAL_DMA_COVER_DEPTH),$(if $(filter sdio,$*),$(FORMAL_SDIO_COVER_DEPTH),$(if $(filter opipsram,$*),$(FORMAL_OPIPSRAM_DEPTH),$(if $(filter ws2812,$*),$(FORMAL_WS2812_DEPTH),$(if $(filter i2c,$*),$(FORMAL_I2C_DEPTH),$(if $(filter clint,$*),$(FORMAL_CLINT_DEPTH),$(if $(filter psram,$*),$(FORMAL_PSRAM_DEPTH),$(FORMAL_DEPTH)))))))) \
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$(if $(filter i2c,$*),--no-vcd) --output $@
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@if [ "$*" = opipsram ]; then sed -i '/^async2sync/i clk2fflogic' $@; fi
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$(FORMAL_DIR)/opipsram/bmc.sby: $(FORMAL_DIR)/opipsram/design.v \
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$(RTL_PATH)/formal/opipsram_formal_props.sv $(FORMAL_SBY_GENERATOR)
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python3 $(FORMAL_SBY_GENERATOR) --top opipsram_formal \
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--input $(FORMAL_DIR)/opipsram/design.v \
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--properties $(RTL_PATH)/formal/opipsram_formal_props.sv \
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--solver $(FORMAL_SOLVER) --mode bmc --depth $(FORMAL_OPIPSRAM_BMC_DEPTH) \
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--output $@
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@sed -i 's/^read_verilog -formal -sv properties.v$$/read_verilog -formal -sv -DOPIPSRAM_BMC properties.v/' $@
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@sed -i '/^async2sync/i clk2fflogic' $@
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$(FORMAL_SOLVER_WRAPPER): $(ROOT_PATH)/scripts/bitwuzla_smt2.py
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@mkdir -p $(@D)
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cp $< $@
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chmod +x $@
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$(FORMAL_DIR)/%/prove.stamp: $(FORMAL_DIR)/%/prove.sby $(FORMAL_SOLVER_WRAPPER)
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool formal-sby-prove \
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--log $(@D)/prove.log --result $(@D)/result-prove.json \
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--env RETROSOC_BITWUZLA=$(FORMAL_BITWUZLA) \
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--env PATH=$(FORMAL_SOLVER_DIR):$(PATH) \
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-- timeout --foreground --kill-after=5s $(if $(filter dma,$*),$(FORMAL_DMA_TIMEOUT),$(if $(filter sdio,$*),$(FORMAL_SDIO_TIMEOUT),$(if $(filter opipsram,$*),$(FORMAL_OPIPSRAM_TIMEOUT),$(if $(filter ws2812,$*),$(FORMAL_WS2812_TIMEOUT),$(if $(filter i2c,$*),$(FORMAL_I2C_TIMEOUT),$(FORMAL_TIMEOUT))))))s $(FORMAL_SBY) \
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-f -d $(@D)/prove $<
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@test "$$(awk '{print $$1}' $(@D)/prove/status)" = PASS
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@touch $@
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$(FORMAL_DIR)/%/cover.stamp: $(FORMAL_DIR)/%/cover.sby $(FORMAL_SOLVER_WRAPPER)
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool formal-sby-cover \
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--log $(@D)/cover.log --result $(@D)/result-cover.json \
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--env RETROSOC_BITWUZLA=$(FORMAL_BITWUZLA) \
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--env PATH=$(FORMAL_SOLVER_DIR):$(PATH) \
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-- timeout --foreground --kill-after=5s $(if $(filter dma,$*),$(FORMAL_DMA_TIMEOUT),$(if $(filter sdio,$*),$(FORMAL_SDIO_TIMEOUT),$(if $(filter opipsram,$*),$(FORMAL_OPIPSRAM_TIMEOUT),$(if $(filter ws2812,$*),$(FORMAL_WS2812_TIMEOUT),$(if $(filter i2c,$*),$(FORMAL_I2C_TIMEOUT),$(FORMAL_TIMEOUT))))))s $(FORMAL_SBY) \
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-f -d $(@D)/cover $<
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@test "$$(awk '{print $$1}' $(@D)/cover/status)" = PASS
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@touch $@
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$(FORMAL_DIR)/opipsram/bmc.stamp: $(FORMAL_DIR)/opipsram/bmc.sby \
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$(FORMAL_SOLVER_WRAPPER)
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool formal-sby-bmc \
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--log $(@D)/bmc.log --result $(@D)/result-bmc.json \
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--env RETROSOC_BITWUZLA=$(FORMAL_BITWUZLA) \
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--env PATH=$(FORMAL_SOLVER_DIR):$(PATH) \
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-- timeout --foreground --kill-after=5s $(FORMAL_OPIPSRAM_TIMEOUT)s $(FORMAL_SBY) \
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-f -d $(@D)/bmc $<
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@test "$$(awk '{print $$1}' $(@D)/bmc/status)" = PASS
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@touch $@
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$(FORMAL_DIR)/opipsram/.stamp: $(FORMAL_DIR)/opipsram/prove.stamp \
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$(FORMAL_DIR)/opipsram/cover.stamp $(FORMAL_DIR)/opipsram/bmc.stamp
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@touch $@
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$(FORMAL_DIR)/%/.stamp: $(FORMAL_DIR)/%/prove.stamp $(FORMAL_DIR)/%/cover.stamp
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@touch $@
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$(FORMAL_RESULT): $(FORMAL_STAMPS) $(FORMAL_RESULT_GENERATOR)
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python3 $(FORMAL_RESULT_GENERATOR) --output $@ \
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$(foreach target,$(FORMAL_TARGETS),--proof $(target)=$(FORMAL_DIR)/$(target))
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formal: $(FORMAL_RESULT) | manifest
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formal-bus: $(FORMAL_DIR)/bus/.stamp | manifest
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formal-rib-adapter: $(FORMAL_DIR)/rib_adapter/.stamp | manifest
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formal-rib2apb: $(FORMAL_DIR)/rib2apb/.stamp | manifest
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formal-sysctrl: $(FORMAL_DIR)/sysctrl/.stamp | manifest
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formal-pll-rcu: $(FORMAL_DIR)/pll_rcu/.stamp | manifest
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formal-gpio: $(FORMAL_DIR)/gpio/.stamp | manifest
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formal-ws2812: $(FORMAL_DIR)/ws2812/.stamp | manifest
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formal-uart: $(FORMAL_DIR)/uart/.stamp | manifest
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formal-i2c: $(FORMAL_DIR)/i2c/.stamp | manifest
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formal-timer: $(FORMAL_DIR)/timer/.stamp | manifest
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formal-clint: $(FORMAL_DIR)/clint/.stamp | manifest
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formal-dvp: $(FORMAL_DIR)/dvp/.stamp | manifest
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formal-i2s: $(FORMAL_DIR)/i2s/.stamp | manifest
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formal-psram: $(FORMAL_DIR)/psram/.stamp | manifest
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formal-opipsram: $(FORMAL_DIR)/opipsram/.stamp | manifest
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formal-dma: $(FORMAL_DIR)/dma/.stamp | manifest
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formal-sdio: $(FORMAL_DIR)/sdio/.stamp | manifest
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formal-doctor:
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$(MAKE) FORMAL=YES SIMU=IVERILOG SYNTH=YOSYS STA=NONE doctor
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formal-clean:
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python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(FORMAL_DIR)
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.PHONY: formal formal-bus formal-rib-adapter formal-rib2apb formal-sysctrl formal-pll-rcu formal-gpio formal-ws2812 formal-uart formal-i2c formal-timer formal-clint formal-dvp formal-i2s formal-psram formal-opipsram formal-dma formal-sdio formal-doctor formal-clean |