mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
a8325ab6b7
- Introduced a new testbench for the SDIO wrapper () to validate APB interactions. - Updated to include IRQ handling for SDIO0 and SDIO1. - Enhanced to account for performance management of SDIO0 and SDIO1. - Modified memory map tests to include SDIO base addresses and performance wait offsets. - Updated pin mapping tests to include SDIO1 signals. - Created a comprehensive suite of SDIO tests () covering various functionalities including CRC, command engine, DMA, and standalone operations. - Added a new test for verifying SDIO register parity against the RTL definition. - Adjusted SOC topology tests to reflect the addition of SDIO in the IRQ and APB fabric.
149 lines
5.8 KiB
Systemverilog
149 lines
5.8 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "gpio_define.svh"
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`include "soc_clock_config.svh"
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`include "user_extensions.svh"
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// GPIO mux reference. The executable source of truth is
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// rtl/mini/integration/soc_topology.json. ALT_ENABLE selects the alternate
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// path, ALT_SELECT chooses ALT0/ALT1, and USER_SELECT gives the pin to User IP.
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//
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// GPIO ALT0 DIR ALT1 DIR
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// ------ --------------------------- ------ ---------------------- ------
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// GPIO00 UART0_CTS_N IN PS2_CLK BIDI
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// GPIO01 UART0_RTS_N OUT PS2_DATA BIDI
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// GPIO02 PWM_SYNC IN WS2812_DATA OUT
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// GPIO03 PWM0 OUT I2C1_SCL BIDI
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// GPIO04 PWM1 OUT I2C1_SDA BIDI
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// GPIO05 PWM2 OUT CLKDIV4 OUT
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// GPIO06 PWM3 OUT SPISD_SCK OUT
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// GPIO07 I2C0_SCL BIDI SPISD_NSS OUT
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// GPIO08 I2C0_SDA BIDI SPISD_MOSI OUT
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// GPIO09 PWM_FAULT IN SPISD_MISO IN
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// GPIO10 I2S_MCLK OUT DVP_PCLK IN
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// GPIO11 I2S_SCLK OUT DVP_HREF IN
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// GPIO12 I2S_LRCK OUT DVP_VSYNC IN
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// GPIO13 I2S_DAC_DATA OUT DVP_DATA0 IN
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// GPIO14 I2S_ADC_DATA IN DVP_DATA1 IN
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// GPIO15 SDIO_SCK OUT DVP_DATA2 IN
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// GPIO16 SDIO_CMD BIDI DVP_DATA3 IN
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// GPIO17 SDIO_DATA0 BIDI DVP_DATA4 IN
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// GPIO18 SDIO_DATA1 BIDI DVP_DATA5 IN
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// GPIO19 SDIO_DATA2 BIDI DVP_DATA6 IN
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// GPIO20 SDIO_DATA3 BIDI DVP_DATA7 IN
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// GPIO21 OPI_PSRAM_SCK OUT QSPI_PSRAM_SCK OUT
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// GPIO22 OPI_PSRAM_CE OUT QSPI_PSRAM_NSS0 OUT
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// GPIO23 OPI_PSRAM_IO0 BIDI QSPI_PSRAM_IO0 BIDI
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// GPIO24 OPI_PSRAM_IO1 BIDI QSPI_PSRAM_IO1 BIDI
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// GPIO25 OPI_PSRAM_IO2 BIDI QSPI_PSRAM_IO2 BIDI
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// GPIO26 OPI_PSRAM_IO3 BIDI QSPI_PSRAM_IO3 BIDI
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// GPIO27 OPI_PSRAM_IO4 BIDI QSPI_PSRAM_NSS1 OUT
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// GPIO28 OPI_PSRAM_IO5 BIDI QSPI_PSRAM_NSS2 OUT
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// GPIO29 OPI_PSRAM_IO6 BIDI QSPI_PSRAM_NSS3 OUT
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// GPIO30 OPI_PSRAM_IO7 BIDI PWM_CAPTURE0 IN
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// GPIO31 OPI_PSRAM_DQS BIDI PWM_CAPTURE1 IN
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//
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// Dedicated SDIO1 pads: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0].
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module retrosoc_asic (
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`include "retrosoc_asic_ports.svh"
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);
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logic s_ext_clk;
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logic s_aud_clk;
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logic s_sys_clkdiv4;
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logic s_timebase_tick;
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`ifdef HAVE_PLL
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logic s_xtal_io;
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`endif
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logic s_sys_clk;
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logic s_ext_rst_n;
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logic s_sys_rst_n;
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logic s_aud_rst_n;
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logic s_wdg_reset_req;
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logic s_jtag_tck;
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logic s_jtag_tms;
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logic s_jtag_tdi;
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logic s_jtag_trst_n;
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logic s_jtag_tdo;
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logic s_uart0_rx;
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logic s_uart0_tx;
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(* keep = "true" *)logic s_test_done;
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(* keep = "true" *)logic s_test_pass;
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(* keep = "true" *)logic [7:0] s_test_code;
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`ifdef HAVE_SRAM_IF
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ram_if u_ram_if ();
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`endif
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gpio_if u_gpio_if ();
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xpi_if u_xpi_if ();
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sdram_if u_sdram_if ();
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sdio_if u_sdio1_if ();
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pll_ctrl_if u_pll_ctrl_if ();
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`include "retrosoc_asic_pad_bindings.svh"
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rcu #(
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.ExtClkHz (`SOC_EXT_CLK_HZ),
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.ClintTimebaseHz(`SOC_CLINT_TIMEBASE_HZ)
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) u_rcu (
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.ext_clk_i (s_ext_clk),
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.aud_clk_i (s_aud_clk),
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.ext_rst_n_i (s_ext_rst_n),
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.wdg_reset_req_i(s_wdg_reset_req),
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`ifdef HAVE_PLL
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.xtal_clk_i (s_xtal_io),
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`endif
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.pll_ctrl (u_pll_ctrl_if),
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.sys_clk_o (s_sys_clk),
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.sys_rst_n_o (s_sys_rst_n),
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.aud_rst_n_o (s_aud_rst_n),
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.sys_clkdiv4_o (s_sys_clkdiv4),
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.timebase_tick_o(s_timebase_tick)
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);
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`ifdef HAVE_SRAM_IF
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onchip_ram u_onchip_ram (
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.clk_i(s_sys_clk),
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.ram (u_ram_if)
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);
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`endif
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retrosoc u_retrosoc (
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.clk_i (s_sys_clk),
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.rst_n_i (s_sys_rst_n),
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.clk_aud_i (s_aud_clk),
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.rst_aud_n_i (s_aud_rst_n),
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.clkdiv4_i (s_sys_clkdiv4),
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.timebase_tick_i(s_timebase_tick),
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.pll_ctrl (u_pll_ctrl_if),
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`ifdef HAVE_SRAM_IF
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.ram (u_ram_if),
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`endif
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.gpio (u_gpio_if),
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.uart_rx_i (s_uart0_rx),
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.uart_tx_o (s_uart0_tx),
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.xpi (u_xpi_if),
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.sdram (u_sdram_if),
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.sdio1 (u_sdio1_if),
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.jtag_tck_i (s_jtag_tck),
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.jtag_tms_i (s_jtag_tms),
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.jtag_tdi_i (s_jtag_tdi),
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.jtag_trst_n_i (s_jtag_trst_n),
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.jtag_tdo_o (s_jtag_tdo),
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.wdg_reset_req_o(s_wdg_reset_req),
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.test_done_o (s_test_done),
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.test_pass_o (s_test_pass),
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.test_code_o (s_test_code)
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);
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endmodule
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