mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
a8325ab6b7
- Introduced a new testbench for the SDIO wrapper () to validate APB interactions. - Updated to include IRQ handling for SDIO0 and SDIO1. - Enhanced to account for performance management of SDIO0 and SDIO1. - Modified memory map tests to include SDIO base addresses and performance wait offsets. - Updated pin mapping tests to include SDIO1 signals. - Created a comprehensive suite of SDIO tests () covering various functionalities including CRC, command engine, DMA, and standalone operations. - Added a new test for verifying SDIO register parity against the RTL definition. - Adjusted SOC topology tests to reflect the addition of SDIO in the IRQ and APB fabric.
53 lines
1.4 KiB
Systemverilog
53 lines
1.4 KiB
Systemverilog
`timescale 1ns / 1ps
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module sdio_clock_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic enable_i = 1'b0;
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logic [15:0] half_period_i = 16'd2;
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logic sck_o;
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logic launch_tick_o;
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logic sample_tick_o;
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logic running_o;
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integer launch_count;
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integer sample_count;
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always #1 clk_i = ~clk_i;
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sdio_clock u_sdio_clock (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.enable_i (enable_i),
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.half_period_i(half_period_i),
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.sck_o (sck_o),
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.launch_tick_o(launch_tick_o),
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.sample_tick_o(sample_tick_o),
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.running_o (running_o)
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);
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always @(posedge clk_i) begin
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if (launch_tick_o) launch_count = launch_count + 1;
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if (sample_tick_o) sample_count = sample_count + 1;
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end
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initial begin
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launch_count = 0;
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sample_count = 0;
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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enable_i = 1'b1;
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repeat (8) @(posedge clk_i);
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if ((launch_count != 2) || (sample_count != 2) || !running_o) begin
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$fatal(1, "phase counts mismatch: launch=%0d sample=%0d running=%b", launch_count,
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sample_count, running_o);
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end
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enable_i = 1'b0;
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repeat (4) @(posedge clk_i);
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if (sck_o || running_o) begin
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$fatal(1, "clock did not stop on a complete low phase");
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end
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$display("SDIO phase clock test passed");
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$finish;
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end
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endmodule
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