mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 22:55:14 +00:00
maksyuki
a87236ae33
- Renamed and to and respectively across various test files and modules. - Updated response codes in tests to use new definitions (). - Added new testbench to validate RIB to RAM interactions. - Created for testing RIBP topology routing. - Adjusted memory map tests to reflect new interface names. - Ensured all references to old interface names were replaced in Python test scripts. - Verified that all test cases pass with the new interface structure.
151 lines
4.2 KiB
Systemverilog
151 lines
4.2 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module ribp_regslice (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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ribp_if.slave ribp_slv,
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ribp_if.master ribp_mst
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// verilog_format: on
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);
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localparam FSM_IDLE = 2'd0;
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localparam FSM_REQ = 2'd1;
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localparam FSM_RESP = 2'd2;
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logic [1:0] s_fsm_d, s_fsm_q;
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logic s_ribp_mst_valid_d, s_ribp_mst_valid_q;
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logic [31:0] s_ribp_mst_addr_d, s_ribp_mst_addr_q;
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logic [31:0] s_ribp_mst_wdata_d, s_ribp_mst_wdata_q;
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logic [3:0] s_ribp_mst_wstrb_d, s_ribp_mst_wstrb_q;
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logic [31:0] s_ribp_mst_rdata_d, s_ribp_mst_rdata_q;
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logic s_ribp_mst_ready_d, s_ribp_mst_ready_q;
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logic s_ribp_mst_resp_err_d, s_ribp_mst_resp_err_q;
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// ribp mst if
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assign ribp_mst.valid = s_ribp_mst_valid_q;
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assign ribp_mst.addr = s_ribp_mst_addr_q;
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assign ribp_mst.wdata = s_ribp_mst_wdata_q;
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assign ribp_mst.wstrb = s_ribp_mst_wstrb_q;
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always_comb begin
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s_fsm_d = s_fsm_q;
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s_ribp_mst_valid_d = s_ribp_mst_valid_q;
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s_ribp_mst_addr_d = s_ribp_mst_addr_q;
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s_ribp_mst_wdata_d = s_ribp_mst_wdata_q;
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s_ribp_mst_wstrb_d = s_ribp_mst_wstrb_q;
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s_ribp_mst_ready_d = s_ribp_mst_ready_q;
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s_ribp_mst_rdata_d = s_ribp_mst_rdata_q;
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s_ribp_mst_resp_err_d = s_ribp_mst_resp_err_q;
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ribp_slv.ready = '0;
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ribp_slv.rdata = '0;
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ribp_slv.resp_err = 1'b0;
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unique case (s_fsm_q)
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FSM_IDLE: begin
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if (ribp_slv.valid) begin
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s_fsm_d = FSM_REQ;
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s_ribp_mst_valid_d = ribp_slv.valid;
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s_ribp_mst_addr_d = ribp_slv.addr;
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s_ribp_mst_wdata_d = ribp_slv.wdata;
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s_ribp_mst_wstrb_d = ribp_slv.wstrb;
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end
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end
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FSM_REQ: begin
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if (ribp_mst.ready) begin
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s_fsm_d = FSM_RESP;
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s_ribp_mst_valid_d = 1'b0;
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s_ribp_mst_ready_d = ribp_mst.ready;
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s_ribp_mst_rdata_d = ribp_mst.rdata;
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s_ribp_mst_resp_err_d = ribp_mst.resp_err;
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end
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end
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FSM_RESP: begin
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s_fsm_d = FSM_IDLE;
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ribp_slv.ready = s_ribp_mst_ready_q;
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ribp_slv.rdata = s_ribp_mst_rdata_q;
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ribp_slv.resp_err = s_ribp_mst_resp_err_q;
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end
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default: begin
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s_fsm_d = s_fsm_q;
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s_ribp_mst_valid_d = s_ribp_mst_valid_q;
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s_ribp_mst_addr_d = s_ribp_mst_addr_q;
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s_ribp_mst_wdata_d = s_ribp_mst_wdata_q;
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s_ribp_mst_wstrb_d = s_ribp_mst_wstrb_q;
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s_ribp_mst_ready_d = s_ribp_mst_ready_q;
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s_ribp_mst_rdata_d = s_ribp_mst_rdata_q;
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s_ribp_mst_resp_err_d = s_ribp_mst_resp_err_q;
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ribp_slv.ready = '0;
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ribp_slv.rdata = '0;
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ribp_slv.resp_err = 1'b0;
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end
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endcase
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end
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dffr #(2) u_fsm_dffr (
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clk_i,
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rst_n_i,
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s_fsm_d,
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s_fsm_q
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);
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dffr #(1) u_ribp_mstr_valid_dffr (
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clk_i,
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rst_n_i,
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s_ribp_mst_valid_d,
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s_ribp_mst_valid_q
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);
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dffr #(32) u_ribp_mst_addr_dffr (
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clk_i,
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rst_n_i,
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s_ribp_mst_addr_d,
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s_ribp_mst_addr_q
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);
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dffr #(32) u_ribp_mst_wdata_dffr (
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clk_i,
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rst_n_i,
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s_ribp_mst_wdata_d,
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s_ribp_mst_wdata_q
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);
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dffr #(4) u_ribp_mst_wstrb_dffr (
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clk_i,
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rst_n_i,
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s_ribp_mst_wstrb_d,
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s_ribp_mst_wstrb_q
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);
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dffr #(32) u_ribp_mst_rdata_dffr (
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clk_i,
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rst_n_i,
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s_ribp_mst_rdata_d,
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s_ribp_mst_rdata_q
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);
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dffr #(1) u_ribp_mst_ready_dffr (
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clk_i,
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rst_n_i,
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s_ribp_mst_ready_d,
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s_ribp_mst_ready_q
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);
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dffr #(1) u_ribp_mst_resp_err_dffr (
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clk_i,
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rst_n_i,
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s_ribp_mst_resp_err_d,
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s_ribp_mst_resp_err_q
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);
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endmodule
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