mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 22:55:14 +00:00
maksyuki
a87236ae33
- Renamed and to and respectively across various test files and modules. - Updated response codes in tests to use new definitions (). - Added new testbench to validate RIB to RAM interactions. - Created for testing RIBP topology routing. - Adjusted memory map tests to reflect new interface names. - Ensured all references to old interface names were replaced in Python test scripts. - Verified that all test cases pass with the new interface structure.
86 lines
2.4 KiB
Systemverilog
86 lines
2.4 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`ifndef RIBP_SDRAM_DEF_SV
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`define RIBP_SDRAM_DEF_SV
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// verilog_format: off
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`define RIBP_SDRAM_CLKDIV 8'h00
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`define RIBP_SDRAM_CFG 8'h04
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// verilog_format: on
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`endif
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module sdram_reg (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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ribp_if.slave ribp,
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output logic [1:0] clkdiv_o
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// verilog_format: on
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);
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// ribp
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logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
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logic s_ribp_ready_d, s_ribp_ready_q;
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logic s_ribp_rdata_en;
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logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
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// register
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logic s_sdram_clkdiv_en;
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logic [1:0] s_sdram_clkdiv_d, s_sdram_clkdiv_q;
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// ribp
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assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
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assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
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assign ribp.ready = s_ribp_ready_q;
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assign ribp.resp_err = 1'b0;
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assign ribp.rdata = s_ribp_rdata_q;
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// reg
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assign clkdiv_o = s_sdram_clkdiv_q;
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assign s_sdram_clkdiv_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SDRAM_CLKDIV;
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assign s_sdram_clkdiv_d = ribp.wdata[1:0];
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dffer #(2) u_sdram_clkdiv_dffer (
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clk_i,
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rst_n_i,
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s_sdram_clkdiv_en,
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s_sdram_clkdiv_d,
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s_sdram_clkdiv_q
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);
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// ribp resp
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assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
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dffr #(1) u_ribp_ready_dffr (
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clk_i,
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rst_n_i,
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s_ribp_ready_d,
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s_ribp_ready_q
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);
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assign s_ribp_rdata_en = s_ribp_rd_hdshk;
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always_comb begin
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s_ribp_rdata_d = s_ribp_rdata_q;
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unique case (ribp.addr[7:0])
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`RIBP_SDRAM_CLKDIV: s_ribp_rdata_d = {30'd0, s_sdram_clkdiv_q};
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default: s_ribp_rdata_d = s_ribp_rdata_q;
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endcase
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end
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dffer #(32) u_ribp_rdata_dffer (
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clk_i,
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rst_n_i,
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s_ribp_rdata_en,
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s_ribp_rdata_d,
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s_ribp_rdata_q
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);
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endmodule
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