Files
retroSoC/rtl/mini/filelist/ip.fl
T
maksyuki a87236ae33 feat: refactor RIB interfaces and update test cases
- Renamed  and  to  and  respectively across various test files and modules.
- Updated response codes in tests to use new definitions ().
- Added new testbench  to validate RIB to RAM interactions.
- Created  for testing RIBP topology routing.
- Adjusted memory map tests to reflect new interface names.
- Ensured all references to old interface names were replaced in Python test scripts.
- Verified that all test cases pass with the new interface structure.
2026-08-04 16:12:22 +08:00

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/ip/ribp/memory/psram_core.sv
/ip/ribp/memory/psram.sv
/ip/ribp/memory/opipsram.sv
/ip/ribp/memory/opipsram_core.sv
/ip/ribp/storage/spisd_init.sv
/ip/ribp/storage/spisd_read.sv
/ip/ribp/storage/spisd_write.sv
/ip/ribp/storage/spisd_reg.sv
/ip/ribp/storage/spisd_cache.sv
/ip/ribp/storage/spisd_core.sv
/ip/ribp/storage/spisd_data.sv
/ip/ribp/storage/spisd.sv
/ip/ribp/storage/sdio.sv
/ip/ribp/serial/i2c_core.sv
/ip/ribp/serial/i2c.sv
/ip/ribp/serial/i2s_reg.sv
/ip/ribp/serial/i2s_clkgen.sv
/ip/ribp/serial/i2s_recv.sv
/ip/ribp/serial/i2s_send.sv
/ip/ribp/serial/i2s_core.sv
/ip/ribp/serial/i2s.sv
/ip/ribp/serial/onewire_core.sv
/ip/ribp/serial/onewire.sv
/ip/ribp/storage/xpi_reg.sv
/ip/ribp/storage/xpi_mm.sv
/ip/ribp/storage/xpi_clkgen.sv
/ip/ribp/storage/xpi_core.sv
/ip/ribp/storage/xpi.sv
/ip/ribp/peripheral/dma_core.sv
/ip/ribp/peripheral/dma.sv
/ip/ribp/peripheral/pll_ctrl_if.sv
/ip/ribp/peripheral/sysctrl.sv
/ip/ribp/peripheral/clint.sv
/ip/ribp/memory/sdram_clkgen.sv
/ip/ribp/memory/sdram_reg.sv
/ip/ribp/memory/sdram_core.sv
/ip/ribp/memory/sdram.sv
/ip/ribp/multimedia/dvp_core.sv
/ip/ribp/multimedia/dvp.sv
/ip/ribp/peripheral/timer.sv
/ip/ribp/serial/uart.sv
/ip/ribp/peripheral/gpio.sv
/ip/ribp/interconnect/ribp2apb.sv
/top/ahbl2ribp.sv
/ip/ribp/interconnect/axi4l2ribp.sv
/ip/ribp/util/async_fifo.sv
/ip/ribp/interconnect/ribp_regslice.sv
/ip/ribp/interconnect/ribp2ribp.sv